sdr_sdram.sxr

IC内核的设计源码！其中包含MP3内核

Inst: SADDR[13] SADDR_13_
Inst: SADDR[14] SADDR_14_
Inst: SADDR[15] SADDR_15_
Inst: SADDR[16] SADDR_16_
Inst: SADDR[17] SADDR_17_
Inst: SADDR[18] SADDR_18_
Inst: SADDR[19] SADDR_19_
Inst: SADDR[20] SADDR_20_
Inst: SADDR[21] SADDR_21_
Inst: SADDR[22] SADDR_22_
Inst: timer[15] timer_15_
Inst: timer_lm15 timer_lm15
Inst: timer[14] timer_14_
Inst: timer_lm14 timer_lm14
Inst: timer[13] timer_13_
Inst: timer_lm13 timer_lm13
Inst: timer[12] timer_12_
Inst: timer_lm12 timer_lm12
Inst: timer[11] timer_11_
Inst: timer_lm11 timer_lm11
Inst: timer[10] timer_10_
Inst: timer_lm10 timer_lm10
Inst: timer[9] timer_9_
Inst: timer_lm9 timer_lm9
Inst: timer[8] timer_8_
Inst: timer_lm8 timer_lm8
Inst: timer[7] timer_7_
Inst: timer_lm7 timer_lm7
Inst: timer[6] timer_6_
Inst: timer_lm6 timer_lm6
Inst: timer[5] timer_5_
Inst: timer_lm5 timer_lm5
Inst: timer[4] timer_4_
Inst: timer_lm4 timer_lm4
Inst: timer[3] timer_3_
Inst: timer_lm3 timer_lm3
Inst: timer[2] timer_2_
Inst: timer_lm2 timer_lm2
Inst: timer[1] timer_1_
Inst: timer_lm1 timer_lm1
Inst: timer[0] timer_0_
Inst: timer_lm0 timer_lm0
Inst: un1_un1_CMD_ACK_i_0 un1_un1_CMD_ACK_i_0
Inst: LOAD_MODE13_0_and2_0_and2 LOAD_MODE13_0_and2_0_and2
Inst: PRECHARGE13_0_and2_0_and2 PRECHARGE13_0_and2_0_and2
Inst: REFRESH13_0_and2_0_and2 REFRESH13_0_and2_0_and2
Inst: READA13_0_and2_0_and2 READA13_0_and2_0_and2
Inst: un1_timer_zero13_1_0_0_L un1_timer_zero13_1_0_0_L
Inst: un1_timer_zero13_1_0_0 un1_timer_zero13_1_0_0
Inst: un1_un1_SC_BL_2_L un1_un1_SC_BL_2_L
Inst: un1_un1_SC_BL_2 un1_un1_SC_BL_2
Inst: un1_timer_zero13_1_0_0_and2.G_189 un1_timer_zero13_1_0_1_189
Inst: un1_timer_zero13_1_0_0_and2.G_191_L un1_timer_zero13_1_0_0_L1
Inst: un1_un1_RESET_N_2 un1_un1_RESET_N_2
Inst: un1_un1_RESET_N_1 un1_un1_RESET_N_1
Inst: un1_un1_RESET_N_3 un1_un1_RESET_N_3
Inst: un1_un1_RESET_N un1_un1_RESET_N
Inst: LOAD_REG110_0_and2_0_and2 LOAD_REG110_0_and2_0_and2
Inst: LOAD_REG110_0_and2_0_and2.G_158 LOAD_REG110_0_and2_0_1_158
Inst: LOAD_REG210_0_and2_0_and2 LOAD_REG210_0_and2_0_and2
Inst: LOAD_REG210_0_and2_0_and2.G_159 LOAD_REG210_0_and2_0_1_159
Inst: WRITEA13_0_and2_0_and2 WRITEA13_0_and2_0_and2
Inst: sc_pm_i sc_pm_i
Inst: ref_req_i_L ref_req_i_L
Inst: G_1_i_and2_0_and2 G_1_i_and2_0_and2
Inst: un1_timer_zero13_1_0_0_and2_cas un1_timer_zero13_1_0_cas1
Inst: un1_timer_zero13_1_0_0_and2_L un1_timer_zero13_1_0_0_and2_L
Inst: un1_timer_zero13_1_0_0_and2_cand un1_timer_zero13_1_0_cand1
Inst: un1_timer_zero13_1_0_0_and2 un1_timer_zero13_1_0_0_and2
Inst: un1_timer_zero13_1_0_0_and2.G_193_cas un1_timer_zero13_1_0_cas2
Inst: un1_timer_zero13_1_0_0_and2.G_193_lut un1_timer_zero13_1_0_lut1
Inst: un1_timer_zero13_1_0_0_and2.G_193_cand un1_timer_zero13_1_0_cand2
Inst: un1_timer_zero13_1_0_0_and2.G_193 un1_timer_zero13_1_0_1_193
Inst: un1_timer_zero13_1_0_0_and2.G_192_cas un1_timer_zero13_1_0_cas3
Inst: un1_timer_zero13_1_0_0_and2.G_192_L un1_timer_zero13_1_0_0_L2
Inst: un1_timer_zero13_1_0_0_and2.G_192_cand un1_timer_zero13_1_0_cand3
Inst: timer_c0_L timer_c0_L
Inst: timer_c0_C timer_c0_C
Inst: timer_c0_cry timer_c0_cry
Inst: timer_c1_L timer_c1_L
Inst: timer_c1_C timer_c1_C
Inst: timer_c1_cry timer_c1_cry
Inst: timer_c2_L timer_c2_L
Inst: timer_c2_C timer_c2_C
Inst: timer_c2_cry timer_c2_cry
Inst: timer_c3_L timer_c3_L
Inst: timer_c3_C timer_c3_C
Inst: timer_c3_cry timer_c3_cry
Inst: timer_c4_L timer_c4_L
Inst: timer_c4_C timer_c4_C
Inst: timer_c4_cry timer_c4_cry
Inst: timer_c5_L timer_c5_L
Inst: timer_c5_C timer_c5_C
Inst: timer_c5_cry timer_c5_cry
Inst: timer_c6_L timer_c6_L
Inst: timer_c6_C timer_c6_C
Inst: timer_c6_cry timer_c6_cry
Inst: timer_c7_L timer_c7_L
Inst: timer_c7_C timer_c7_C
Inst: timer_c7_cry timer_c7_cry
Inst: timer_c8_L timer_c8_L
Inst: timer_c8_C timer_c8_C
Inst: timer_c8_cry timer_c8_cry
Inst: timer_c9_L timer_c9_L
Inst: timer_c9_C timer_c9_C
Inst: timer_c9_cry timer_c9_cry
Inst: timer_c10_L timer_c10_L
Inst: timer_c10_C timer_c10_C
Inst: timer_c10_cry timer_c10_cry
Inst: timer_c11_L timer_c11_L
Inst: timer_c11_C timer_c11_C
Inst: timer_c11_cry timer_c11_cry
Inst: timer_c12_L timer_c12_L
Inst: timer_c12_C timer_c12_C
Inst: timer_c12_cry timer_c12_cry
Inst: timer_c13_L timer_c13_L
Inst: timer_c13_C timer_c13_C
Inst: timer_c13_cry timer_c13_cry
Inst: timer_c14_L timer_c14_L
Inst: timer_c14_C timer_c14_C
Inst: timer_c14_cry timer_c14_cry
Inst: timer_c15_L timer_c15_L
Net: sc_pm_i sc_pm_i
Net: G_159 G_159
Net: G_158 G_158
Net: G_191 G_191
Net: G_189 G_189
Net: G_192 G_192
Net: I_115 I_115
Net: un1_un1_SC_BL_2 un1_un1_SC_BL_2
Net: G_193 G_193
Net: REF_ACK REF_ACK
Net: CMD[1] CMD_1_
Net: CMD[2] CMD_2_
Net: CMD[0] CMD_0_
Net: CM_ACK_i CM_ACK_i
Net: SC_PM SC_PM
Net: LOAD_MODE LOAD_MODE
Net: LOAD_MODE13_0_and2_0_and2 LOAD_MODE13_0_and2_0_and2
Net: PRECHARGE PRECHARGE
Net: PRECHARGE13_0_and2_0_and2 PRECHARGE13_0_and2_0_and2
Net: READA READA
Net: READA13_0_and2_0_and2 READA13_0_and2_0_and2
Net: REFRESH REFRESH
Net: REFRESH13_0_and2_0_and2 REFRESH13_0_and2_0_and2
Net: WRITEA WRITEA
Net: WRITEA13_0_and2_0_and2 WRITEA13_0_and2_0_and2
Net: LOAD_REG210_0_and2_0_and2 LOAD_REG210_0_and2_0_and2
Net: un1_un1_RESET_N un1_un1_RESET_N
Net: un1_un1_RESET_N_3 un1_un1_RESET_N_3
Net: LOAD_REG110_0_and2_0_and2 LOAD_REG110_0_and2_0_and2
Net: un1_un1_RESET_N_1 un1_un1_RESET_N_1
Net: un1_un1_RESET_N_2 un1_un1_RESET_N_2
Net: CMDACK CMDACK
Net: un1_un1_CMD_ACK_i_0 un1_un1_CMD_ACK_i_0
Net: REF_REQ REF_REQ
Net: un1_timer_zero13_1_0_0_and2 un1_timer_zero13_1_0_0_and2
Net: un1_timer_zero13_1_0_0 un1_timer_zero13_1_0_0
Net: un1_LOAD_REG210 un1_LOAD_REG210
Net: SC_BL[0] SC_BL_0_
Net: SC_BL[1] SC_BL_1_
Net: SC_BL[2] SC_BL_2_
Net: SC_BL[3] SC_BL_3_
Net: SC_RC[0] SC_RC_0_
Net: SC_RC[1] SC_RC_1_
Net: un1_LOAD_REG110 un1_LOAD_REG110
Net: SADDR[0] SADDR_0_
Net: ADDR[0] ADDR_0_
Net: SADDR[1] SADDR_1_
Net: ADDR[1] ADDR_1_
Net: SADDR[2] SADDR_2_
Net: ADDR[2] ADDR_2_
Net: SADDR[3] SADDR_3_
Net: ADDR[3] ADDR_3_
Net: SADDR[4] SADDR_4_
Net: ADDR[4] ADDR_4_
Net: SADDR[5] SADDR_5_
Net: ADDR[5] ADDR_5_
Net: SADDR[6] SADDR_6_
Net: ADDR[6] ADDR_6_
Net: SADDR[7] SADDR_7_
Net: ADDR[7] ADDR_7_
Net: SADDR[8] SADDR_8_
Net: ADDR[8] ADDR_8_
Net: SADDR[9] SADDR_9_
Net: ADDR[9] ADDR_9_
Net: SADDR[10] SADDR_10_
Net: ADDR[10] ADDR_10_
Net: SADDR[11] SADDR_11_
Net: ADDR[11] ADDR_11_
Net: SADDR[12] SADDR_12_
Net: ADDR[12] ADDR_12_
Net: SADDR[13] SADDR_13_
Net: ADDR[13] ADDR_13_
Net: SADDR[14] SADDR_14_
Net: ADDR[14] ADDR_14_
Net: SADDR[15] SADDR_15_
Net: ADDR[15] ADDR_15_
Net: SADDR[16] SADDR_16_
Net: ADDR[16] ADDR_16_
Net: SADDR[17] SADDR_17_
Net: ADDR[17] ADDR_17_
Net: SADDR[18] SADDR_18_
Net: ADDR[18] ADDR_18_
Net: SADDR[19] SADDR_19_
Net: ADDR[19] ADDR_19_
Net: SADDR[20] SADDR_20_
Net: ADDR[20] ADDR_20_
Net: SADDR[21] SADDR_21_
Net: ADDR[21] ADDR_21_
Net: SADDR[22] SADDR_22_
Net: ADDR[22] ADDR_22_
Net: timer_lm15 timer_lm15
Net: REF_PER[15] REF_PER_15_
Net: timer[15] timer_15_
Net: timer_lm14 timer_lm14
Net: REF_PER[14] REF_PER_14_
Net: timer_c14_COUT timer_c14_COUT
Net: timer[14] timer_14_
Net: timer_lm13 timer_lm13
Net: REF_PER[13] REF_PER_13_
Net: timer_c13_COUT timer_c13_COUT
Net: timer[13] timer_13_
Net: timer_lm12 timer_lm12
Net: REF_PER[12] REF_PER_12_
Net: timer_c12_COUT timer_c12_COUT
Net: timer[12] timer_12_
Net: timer_lm11 timer_lm11
Net: REF_PER[11] REF_PER_11_
Net: timer_c11_COUT timer_c11_COUT
Net: timer[11] timer_11_
Net: timer_lm10 timer_lm10
Net: REF_PER[10] REF_PER_10_
Net: timer_c10_COUT timer_c10_COUT
Net: timer[10] timer_10_
Net: timer_lm9 timer_lm9
Net: REF_PER[9] REF_PER_9_
Net: timer_c9_COUT timer_c9_COUT
Net: timer[9] timer_9_
Net: timer_lm8 timer_lm8
Net: REF_PER[8] REF_PER_8_
Net: timer_c8_COUT timer_c8_COUT
Net: timer[8] timer_8_
Net: timer_lm7 timer_lm7
Net: REF_PER[7] REF_PER_7_
Net: timer_c7_COUT timer_c7_COUT
Net: timer[7] timer_7_
Net: timer_lm6 timer_lm6
Net: REF_PER[6] REF_PER_6_
Net: timer_c6_COUT timer_c6_COUT
Net: timer[6] timer_6_
Net: timer_lm5 timer_lm5
Net: REF_PER[5] REF_PER_5_
Net: timer_c5_COUT timer_c5_COUT
Net: timer[5] timer_5_
Net: timer_lm4 timer_lm4
Net: REF_PER[4] REF_PER_4_
Net: timer_c4_COUT timer_c4_COUT
Net: timer[4] timer_4_
Net: timer_lm3 timer_lm3
Net: REF_PER[3] REF_PER_3_
Net: timer_c3_COUT timer_c3_COUT
Net: timer[3] timer_3_
Net: timer_lm2 timer_lm2
Net: REF_PER[2] REF_PER_2_
Net: timer_c2_COUT timer_c2_COUT
Net: timer[2] timer_2_
Net: timer_lm1 timer_lm1
Net: REF_PER[1] REF_PER_1_
Net: timer_c1_COUT timer_c1_COUT
Net: timer[1] timer_1_
Net: CLK CLK
Net: RESET_N RESET_N
Net: G_1_i_and2_0_and2 G_1_i_and2_0_and2
Net: timer_lm0 timer_lm0
Net: REF_PER[0] REF_PER_0_
Net: ref_req_i ref_req_i
Net: timer_c0_COUT timer_c0_COUT
Net: timer[0] timer_0_
Net: GND GND
Net: VCC VCC
Net: un1_timer_zero13_1_0_0_L un1_timer_zero13_1_0_0_L
Net: un1_un1_SC_BL_2_L un1_un1_SC_BL_2_L
Net: N_1 N_1
Net: un1_timer_zero13_1_0_0_and2_L un1_timer_zero13_1_0_0_and2_L
Net: N_2 N_2
Net: N_3 N_3
Net: un1_timer_zero13_1_0_0_and2.G_193_lut un1_timer_zero13_1_0_lut2
Net: N_4 N_4
Net: N_5 N_5
Net: un1_timer_zero13_1_0_0_and2.G_192_L un1_timer_zero13_1_0_0_L5
Net: timer_c0_C timer_c0_C
Net: timer_c0_L timer_c0_L
Net: timer_c1_C timer_c1_C
Net: timer_c1_L timer_c1_L
Net: timer_c2_C timer_c2_C
Net: timer_c2_L timer_c2_L
Net: timer_c3_C timer_c3_C
Net: timer_c3_L timer_c3_L
Net: timer_c4_C timer_c4_C
Net: timer_c4_L timer_c4_L
Net: timer_c5_C timer_c5_C
Net: timer_c5_L timer_c5_L
Net: timer_c6_C timer_c6_C
Net: timer_c6_L timer_c6_L
Net: timer_c7_C timer_c7_C
Net: timer_c7_L timer_c7_L
Net: timer_c8_C timer_c8_C
Net: timer_c8_L timer_c8_L
Net: timer_c9_C timer_c9_C
Net: timer_c9_L timer_c9_L
Net: timer_c10_C timer_c10_C
Net: timer_c10_L timer_c10_L
Net: timer_c11_C timer_c11_C
Net: timer_c11_L timer_c11_L
Net: timer_c12_C timer_c12_C
Net: timer_c12_L timer_c12_L
Net: timer_c13_C timer_c13_C
Net: timer_c13_L timer_c13_L
Net: timer_c14_C timer_c14_C
Net: timer_c14_L timer_c14_L
Net: timer_c15_L timer_c15_L
EndView control_interface control_interface
BeginView S_DFFE S_DFFE
Inst: clr clr
Inst: pre pre
Inst: r r
Inst: Q Q
Net: Q Q
Net: D D
Net: CLK CLK
Net: CLRN CLRN
Net: PRN PRN
Net: ENA ENA
Net: clr clr
Net: pre pre
Net: r r
EndView S_DFFE S_DFFE
BeginView S_MUX21 S_MUX21
Inst: SELN SELN
Inst: m0 m0
Inst: m1 m1
Inst: Z Z
Net: Z Z
Net: I0 I0
Net: I1 I1
Net: SEL SEL
Net: SELN SELN
Net: m0 m0
Net: m1 m1
EndView S_MUX21 S_MUX21
BeginView LUT LUT
Net: false false
Net: IN1 IN1
Net: IN2 IN2
Net: IN3 IN3
Net: IN4 IN4
EndView LUT LUT
BeginView L2_E L2_E
Inst: G_1 G_1
Net: I0 I0
Net: I1 I1
Net: Z Z
EndView L2_E L2_E
BeginView LCELL LCELL
Inst: b b
Net: A_OUT A_OUT
Net: A_IN A_IN
EndView LCELL LCELL
BeginView L2_1 L2_1
Inst: G_1 G_1
Inst: G_2 G_2
Inst: G_3 G_3
Net: I0 I0
Net: I1 I1
Net: N_2 N_2
Net: N_3 N_3
Net: Z Z
EndView L2_1 L2_1
BeginView L4_1 L4_1
Inst: G_1 G_1
Inst: G_2 G_2
Inst: G_3 G_3
Inst: G_4 G_4
Inst: G_5 G_5
Inst: G_6 G_6
Inst: G_7 G_7
Net: I0 I0
Net: I1 I1
Net: I2 I2
Net: I3 I3
Net: N_2 N_2
Net: N_3 N_3
Net: N_4 N_4
Net: N_5 N_5
Net: N_6 N_6
Net: N_7 N_7
Net: Z Z
EndView L4_1 L4_1
BeginView CASCADE CASCADE
Inst: b b
Net: A_OUT A_OUT
Net: A_IN A_IN
EndView CASCADE CASCADE
BeginView L3_70 L3_70
Inst: G_1 G_1
Inst: G_2 G_2
Inst: G_3 G_3
Inst: G_4 G_4
Net: I0 I0
Net: I1 I1
Net: I2 I2
Net: N_2 N_2
Net: N_3 N_3
Net: N_4 N_4
Net: Z Z
EndView L3_70 L3_70
BeginView L2_9 L2_9
Inst: G_1 G_1
Inst: G_2 G_2
Net: I0 I0
Net: I1 I1
Net: N_2 N_2
Net: Z Z
EndView L2_9 L2_9
BeginView CARRY CARRY
Inst: b b
Net: A_OUT A_OUT
Net: A_IN A_IN
EndView CARRY CARRY
BeginView command command
Inst: G_134_lc G_134_lc
Inst: G_136_lc G_136_lc
Inst: rp_shift_i[2] rp_shift_i_2_
Inst: rp_shift_i[1] rp_shift_i_1_
Inst: rp_shift_i[0] rp_shift_i_0_
Inst: command_delay_i[7] command_delay_i_7_
Inst: command_delay_i[6] command_delay_i_6_
Inst: command_delay_i[5] command_delay_i_5_
Inst: command_delay_i[4] command_delay_i_4_
Inst: command_delay_i[3] command_delay_i_3_
Inst: command_delay_i[2] command_delay_i_2_
Inst: command_delay_i[1] command_delay_i_1_
Inst: command_delay_i[0] command_delay_i_0_
Inst: oe4_i oe4_i
Inst: CM_ACK_i CM_ACK_i
Inst: do_rw_i do_rw_i
Inst: command_done_i command_done_i
Inst: rp_done_i rp_done_i
Inst: CKE CKE
Inst: do_load_mode do_load_mode
Inst: do_precharge do_precharge
Inst: do_writea1 do_writea1
Inst: do_reada do_reada
Inst: do_writea do_writea
Inst: oe3 oe3
Inst: oe2 oe2
Inst: do_refresh do_refresh
Inst: rw_flag rw_flag
Inst: oe1 oe1
Inst: REF_ACK REF_ACK
Inst: OE OE
Inst: WE_N WE_N
Inst: CAS_N CAS_N
Inst: RAS_N RAS_N
Inst: oe_shift[0] oe_shift_0_
Inst: oe_shift[1] oe_shift_1_
Inst: oe_shift[2] oe_shift_2_
Inst: oe_shift[3] oe_shift_3_
Inst: oe_shift[4] oe_shift_4_
Inst: oe_shift[5] oe_shift_5_
Inst: oe_shift[6] oe_shift_6_
Inst: SA[0] SA_0_
Inst: SA[1] SA_1_
Inst: SA[2] SA_2_
Inst: SA[3] SA_3_
Inst: SA[4] SA_4_
Inst: SA[5] SA_5_
Inst: SA[6] SA_6_
Inst: SA[7] SA_7_
Inst: SA[8] SA_8_
Inst: SA[9] SA_9_
Inst: SA[10] SA_10_
Inst: SA[11] SA_11_
Inst: CS_N[0] CS_N_0_
Inst: CS_N[1] CS_N_1_
Inst: BA[0] BA_0_