sdr_sdram.srs

IC内核的设计源码！其中包含MP3内核

#
#
#
# Created by Synplify Verilog HDL Compiler version 6.2.0, Build 097R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Thu Oct 11 09:07:11 2001
#
#
#OPTIONS:"|-ram|-IC:\\synplicity\\synplify\\lib|-autosm|-fid2|-sharing|on|-encrypt|-ui"
#CUR:"C:\\synplicity\\synplify\\bin\\c_ver.exe":987407294l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\command.v":1002727784l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\params.v":962871140l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\control_interface.v":964769540l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\params.v":962871140l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\params.v":962871140l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\sdr_data_path.v":964769564l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\params.v":962871140l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\sdr_sdram.v":1002762256l
#CUR:"g:\\hdl_doc\\ip\\sdram\\source\\params.v":962871140l
f "g:\hdl_doc\ip\sdram\source\command.v"; # file 0
f "g:\hdl_doc\ip\sdram\source\params.v"; # file 1
f "g:\hdl_doc\ip\sdram\source\control_interface.v"; # file 2
f "g:\hdl_doc\ip\sdram\source\params.v"; # file 3
f "g:\hdl_doc\ip\sdram\source\params.v"; # file 4
f "g:\hdl_doc\ip\sdram\source\sdr_data_path.v"; # file 5
f "g:\hdl_doc\ip\sdram\source\params.v"; # file 6
f "g:\hdl_doc\ip\sdram\source\sdr_sdram.v"; # file 7
f "g:\hdl_doc\ip\sdram\source\params.v"; # file 8
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