📄 sdr_sdram.srr
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DATAOUT[4] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[5] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[6] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[7] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[8] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[9] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[10] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[11] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[12] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[13] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[14] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[15] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[16] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[17] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[18] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[19] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[20] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[21] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[22] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[23] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[24] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[25] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[26] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[27] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[28] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[29] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[30] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[31] CLK [rising] 0.0 1.5 1000.0 998.5
DQM[0] CLK [rising] 0.0 1.5 1000.0 998.5
DQM[1] CLK [rising] 0.0 1.5 1000.0 998.5
DQM[2] CLK [rising] 0.0 1.5 1000.0 998.5
DQM[3] CLK [rising] 0.0 1.5 1000.0 998.5
DQ[0] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[1] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[2] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[3] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[4] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[5] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[6] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[7] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[8] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[9] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[10] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[11] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[12] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[13] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[14] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[15] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[16] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[17] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[18] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[19] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[20] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[21] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[22] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[23] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[24] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[25] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[26] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[27] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[28] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[29] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[30] CLK [rising] 0.0 0.0 1000.0 1000.0
DQ[31] CLK [rising] 0.0 0.0 1000.0 1000.0
RAS_N CLK [rising] 0.0 1.5 1000.0 998.5
SA[0] CLK [rising] 0.0 1.5 1000.0 998.5
SA[1] CLK [rising] 0.0 1.5 1000.0 998.5
SA[2] CLK [rising] 0.0 1.5 1000.0 998.5
SA[3] CLK [rising] 0.0 1.5 1000.0 998.5
SA[4] CLK [rising] 0.0 1.5 1000.0 998.5
SA[5] CLK [rising] 0.0 1.5 1000.0 998.5
SA[6] CLK [rising] 0.0 1.5 1000.0 998.5
SA[7] CLK [rising] 0.0 1.5 1000.0 998.5
SA[8] CLK [rising] 0.0 1.5 1000.0 998.5
SA[9] CLK [rising] 0.0 1.5 1000.0 998.5
SA[10] CLK [rising] 0.0 1.5 1000.0 998.5
SA[11] CLK [rising] 0.0 1.5 1000.0 998.5
WE_N CLK [rising] 0.0 1.5 1000.0 998.5
===============================================================================
Detailed Timing Report for clock : CLK
*******************************************
Requested Period 1000.0 ns
Estimated Period 6.9 ns
Worst Slack 993.1 ns
Start Points for Paths with Slack Worse than 993.8 ns :
Arrival
Instance Type Pin Net Time Slack
----------------------------------------------------------------------------------------
control1.SC_BL[1] S_DFFE Q control1.SC_BL[1] 1.8 993.1
command1.do_precharge S_DFF Q command1.do_precharge 1.9 993.1
command1.do_load_mode S_DFF Q command1.do_load_mode 1.8 993.1
control1.SC_BL[0] S_DFFE Q control1.SC_BL[0] 1.8 993.2
control1.SC_BL[2] S_DFFE Q control1.SC_BL[2] 1.5 993.2
control1.SC_BL[3] S_DFFE Q control1.SC_BL[3] 1.5 993.3
control1.timer[0] S_DFFE Q control1.timer[0] 1.5 993.7
command1.do_reada S_DFF Q command1.do_reada 2.0 993.7
command1.do_refresh S_DFF Q command1.do_refresh 2.0 993.7
control1.timer[5] S_DFFE Q control1.timer[5] 1.5 993.7
========================================================================================
End Points for Paths with Slack Worse than 993.8 ns :
Required
Instance Type Pin Net Time Slack
------------------------------------------------------------------------------------------------------------
control1.REF_REQ S_DFFE ENA control1.un1_timer_zero13_1_0_0 999.4 993.1
command1.REF_ACK S_DFFE ENA command1.CM_ACK14_i 999.4 993.1
command1.rw_flag S_DFFE ENA command1.N_229_i 999.4 993.1
command1.RAS_N S_DFF D command1.RAS_N_13_0 999.5 993.2
command1.command_delay_i[0] S_DFF D command1.command_delay_7_i_and2[0] 999.5 993.2
command1.command_delay_i[1] S_DFF D command1.command_delay_7_i_and2[1] 999.5 993.2
command1.command_delay_i[2] S_DFF D command1.command_delay_7_i_and2[2] 999.5 993.2
command1.command_delay_i[3] S_DFF D command1.command_delay_7_i_and2[3] 999.5 993.2
command1.command_delay_i[4] S_DFF D command1.command_delay_7_i_and2[4] 999.5 993.2
command1.command_delay_i[5] S_DFF D command1.command_delay_7_i_and2[5] 999.5 993.2
============================================================================================================
A Critical Path with worst case slack = 993.1 ns:
The start and the end point of this path are clocked by the CLK [rising]
Instance/Net Pin Pin Arrival Delta Fan
Name Type Name Dir Time Delay Out
-------------------------------------------------------------------------------------------------
sdr_sdram View
control1.SC_BL[1] S_DFFE Q Out 1.8 1.8
control1.SC_BL[1] Net 4
I_115 S_LUT I1 In 1.8
I_115 S_LUT OUT Out 4.2 2.4
I_115 Net 4
control1.un1_timer_zero13_1_0_0_and2 S_CAS I0 In 4.2
control1.un1_timer_zero13_1_0_0_and2 S_CAS OUT Out 5.8 1.6
control1.un1_timer_zero13_1_0_0_and2 Net 2
control1.un1_timer_zero13_1_0_0 S_LUT I1 In 5.8
control1.un1_timer_zero13_1_0_0 S_LUT OUT Out 6.3 0.5
control1.un1_timer_zero13_1_0_0 Net 1
control1.REF_REQ S_DFFE ENA In 6.3
=================================================================================================
Setup requirement on this path is 0.6 ns.
##### END TIMING REPORT #####
Found clock CLK with period 1000ns
---------------------------------------
Resource Usage Report
Synplify Pro is performing all technology mapping.
Post place and route resource use may vary a small
amount due to logic cell replication and register packing
decisions during place and route.
Design view:work.sdr_sdram(verilog)
Selecting part ep1k10tc100-1
Logic resources: 323 LCs of 576 (56%)
Number of Nets: 531
Number of Inputs: 1719
Register bits: 285 (58 using enable)
EABs: 0 (0% of 3)
I/O cells: 153
Details:
Cells in logic mode: 91
Cells in arith mode: 0
Cells in cascade mode: 7
Cells in counter mode: 16
DFFs with no input combinational logic: 209 (uses cell for routing)
LUTs driving both DFF and logic: 54
All Constraints processed!
All Constraints processed!
Mapper successful!
Process took 6.239 seconds realtime, 6.309 seconds cputime
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