📄 sdr_sdram.srr
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$ Start of Compile
#Thu Oct 11 09:07:09 2001
Synplicity Verilog Compiler, version 6.2.0, Build 097R, built Apr 16 2001
Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved
@I::"g:\hdl_doc\ip\sdram\source\command.v"
@I:"g:\hdl_doc\ip\sdram\source\command.v":"g:\hdl_doc\ip\sdram\source\params.v"
@I::"g:\hdl_doc\ip\sdram\source\control_interface.v"
@I:"g:\hdl_doc\ip\sdram\source\control_interface.v":"g:\hdl_doc\ip\sdram\source\params.v"
@I::"g:\hdl_doc\ip\sdram\source\params.v"
@I::"g:\hdl_doc\ip\sdram\source\sdr_data_path.v"
@I:"g:\hdl_doc\ip\sdram\source\sdr_data_path.v":"g:\hdl_doc\ip\sdram\source\params.v"
@I::"g:\hdl_doc\ip\sdram\source\sdr_sdram.v"
@I:"g:\hdl_doc\ip\sdram\source\sdr_sdram.v":"g:\hdl_doc\ip\sdram\source\params.v"
Verilog syntax check successful!
File g:\hdl_doc\ip\sdram\source\altclklock.v changed - recompiling
Selecting top level module sdr_sdram
Synthesizing module control_interface
@W:"g:\hdl_doc\ip\sdram\source\control_interface.v":93:0:93:5|Register LOAD_REG1 with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
@W:"g:\hdl_doc\ip\sdram\source\control_interface.v":93:0:93:5|Register LOAD_REG2 with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
Synthesizing module command
@W:"g:\hdl_doc\ip\sdram\source\command.v":101:32:101:37|No assignment to do_act
@W:"g:\hdl_doc\ip\sdram\source\command.v":220:0:220:5|Ignoring missing reset value for signal oe4. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\command.v":220:0:220:5|Ignoring missing reset value for signal oe3. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\command.v":125:0:125:5|Ignoring missing reset value for signal do_writea1. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\command.v":220:0:220:5|Optimizing register bit oe_shift[7] to a constant 0
@W:"g:\hdl_doc\ip\sdram\source\command.v":281:0:281:5|Optimizing register bit rw_shift[3] to a constant 0
@W:"g:\hdl_doc\ip\sdram\source\command.v":281:0:281:5|Optimizing register bit rw_shift[2] to a constant 0
@W:"g:\hdl_doc\ip\sdram\source\command.v":53:32:53:34|Input NOP is unused
@W:"g:\hdl_doc\ip\sdram\source\command.v":59:32:59:36|Input SC_CL is unused
@W:"g:\hdl_doc\ip\sdram\source\command.v":61:32:61:37|Input SC_RRD is unused
Synthesizing module sdr_data_path
@W:"g:\hdl_doc\ip\sdram\source\sdr_data_path.v":58:0:58:5|Ignoring missing reset value for signal DQM[3:0]. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\sdr_data_path.v":35:32:35:33|Input OE is unused
Synthesizing module sdr_sdram
@END
Process took 0.901 seconds realtime, 0.991 seconds cputime
Synplicity Altera Technology Mapper, version 6.2.0, Build 096R, built Apr 13 2001
Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved
Automatic dissolve at startup in view:work.sdr_sdram(verilog) of data_path1(sdr_data_path)
@N:"g:\hdl_doc\ip\sdram\source\control_interface.v":207:0:207:5|Found counter in view:work.control_interface(verilog) inst timer[15:0]
Automatic dissolve during optimization of view:work.sdr_sdram(verilog) of control1(control_interface)
Created 2 cliques with a total of 10 instances along critical paths
Created 2 cliques with a total of 10 instances along critical paths
Found clock CLK with period 1000ns
##### START TIMING REPORT #####
Performance Summary
*********************
Requested Estimated Requested Estimated
Clock Frequency Frequency Period Period Slack
-----------------------------------------------------------------------
CLK 1.0 MHz 144.9 MHz 1000.0 6.9 993.1
=======================================================================
Interface Information
***********************
Input Ports:
Port Reference User Arrival Required
Name Clock Constraint Time Time Slack
-----------------------------------------------------------------------------
ADDR[0] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[1] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[2] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[3] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[4] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[5] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[6] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[7] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[8] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[9] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[10] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[11] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[12] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[13] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[14] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[15] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[16] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[17] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[18] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[19] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[20] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[21] CLK [rising] 0.0 0.0 999.5 999.5
ADDR[22] CLK [rising] 0.0 0.0 999.5 999.5
CLK System 0.0 0.0 >2000.0 NA
CMD[0] CLK [rising] 0.0 0.0 997.3 997.3
CMD[1] CLK [rising] 0.0 0.0 998.4 998.4
CMD[2] CLK [rising] 0.0 0.0 997.3 997.3
DATAIN[0] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[1] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[2] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[3] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[4] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[5] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[6] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[7] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[8] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[9] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[10] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[11] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[12] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[13] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[14] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[15] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[16] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[17] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[18] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[19] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[20] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[21] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[22] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[23] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[24] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[25] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[26] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[27] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[28] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[29] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[30] CLK [rising] 0.0 0.0 999.5 999.5
DATAIN[31] CLK [rising] 0.0 0.0 999.5 999.5
DM[0] CLK [rising] 0.0 0.0 999.5 999.5
DM[1] CLK [rising] 0.0 0.0 999.5 999.5
DM[2] CLK [rising] 0.0 0.0 999.5 999.5
DM[3] CLK [rising] 0.0 0.0 999.5 999.5
DQ[0] CLK [rising] 0.0 0.0 999.5 999.5
DQ[1] CLK [rising] 0.0 0.0 999.5 999.5
DQ[2] CLK [rising] 0.0 0.0 999.5 999.5
DQ[3] CLK [rising] 0.0 0.0 999.5 999.5
DQ[4] CLK [rising] 0.0 0.0 999.5 999.5
DQ[5] CLK [rising] 0.0 0.0 999.5 999.5
DQ[6] CLK [rising] 0.0 0.0 999.5 999.5
DQ[7] CLK [rising] 0.0 0.0 999.5 999.5
DQ[8] CLK [rising] 0.0 0.0 999.5 999.5
DQ[9] CLK [rising] 0.0 0.0 999.5 999.5
DQ[10] CLK [rising] 0.0 0.0 999.5 999.5
DQ[11] CLK [rising] 0.0 0.0 999.5 999.5
DQ[12] CLK [rising] 0.0 0.0 999.5 999.5
DQ[13] CLK [rising] 0.0 0.0 999.5 999.5
DQ[14] CLK [rising] 0.0 0.0 999.5 999.5
DQ[15] CLK [rising] 0.0 0.0 999.5 999.5
DQ[16] CLK [rising] 0.0 0.0 999.5 999.5
DQ[17] CLK [rising] 0.0 0.0 999.5 999.5
DQ[18] CLK [rising] 0.0 0.0 999.5 999.5
DQ[19] CLK [rising] 0.0 0.0 999.5 999.5
DQ[20] CLK [rising] 0.0 0.0 999.5 999.5
DQ[21] CLK [rising] 0.0 0.0 999.5 999.5
DQ[22] CLK [rising] 0.0 0.0 999.5 999.5
DQ[23] CLK [rising] 0.0 0.0 999.5 999.5
DQ[24] CLK [rising] 0.0 0.0 999.5 999.5
DQ[25] CLK [rising] 0.0 0.0 999.5 999.5
DQ[26] CLK [rising] 0.0 0.0 999.5 999.5
DQ[27] CLK [rising] 0.0 0.0 999.5 999.5
DQ[28] CLK [rising] 0.0 0.0 999.5 999.5
DQ[29] CLK [rising] 0.0 0.0 999.5 999.5
DQ[30] CLK [rising] 0.0 0.0 999.5 999.5
DQ[31] CLK [rising] 0.0 0.0 999.5 999.5
RESET_N CLK [rising] 0.0 0.0 997.2 997.2
=============================================================================
Output Ports:
Port Reference User Arrival Required
Name Clock Constraint Time Time Slack
-------------------------------------------------------------------------------
BA[0] CLK [rising] 0.0 1.5 1000.0 998.5
BA[1] CLK [rising] 0.0 1.5 1000.0 998.5
CAS_N CLK [rising] 0.0 1.5 1000.0 998.5
CKE CLK [rising] 0.0 1.5 1000.0 998.5
CMDACK CLK [rising] 0.0 1.8 1000.0 998.2
CS_N[0] CLK [rising] 0.0 1.5 1000.0 998.5
CS_N[1] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[0] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[1] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[2] CLK [rising] 0.0 1.5 1000.0 998.5
DATAOUT[3] CLK [rising] 0.0 1.5 1000.0 998.5
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