sdr_sdram.sat

IC内核的设计源码！其中包含MP3内核

define_design_name {sdr_sdram}
define_synthesis -family ACEX1K
define_synthesis -device {ep1k10tc100-1}
define_synthesis -style WYSIWYG
define_synthesis -inverter_push_back OFF
clear_auto_cliques
define_clock {|CLK} -period 1000.000
puts {All Constraints processed!}