📄 sdr_sdram.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\hdl_doc\ip\sdram\source\rev_1\sdr_sdram.rpt
sdr_sdram
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 06 DFFE + 0 1 1 0 BA_0_ (BA4)
- 4 - A 17 DFFE + 0 1 1 0 BA_1_ (BA5)
- 3 - A 01 DFFE + 0 1 1 0 CAS_N1
- 1 - F 33 DFFE + 0 1 1 0 CKE1
- 7 - A 06 DFFE + 1 3 0 1 |command:command1|BA_0_ (|command:command1|BA2)
- 2 - A 17 DFFE + 1 3 0 1 |command:command1|BA_1_ (|command:command1|BA3)
- 7 - A 01 DFFE + 1 3 0 1 |command:command1|CAS_N1
- 2 - F 33 DFFE + 1 0 0 1 |command:command1|CKE1
- 3 - E 17 DFFE + ! 0 2 0 1 |command:command1|CM_ACK_i1
- 2 - E 17 OR2 0 2 0 1 |command:command1|CM_ACK13_0_and2~2
- 6 - E 13 OR2 0 3 0 1 |command:command1|CM_ACK14_i~6
- 1 - A 02 DFFE + ! 0 2 0 6 |command:command1|command_delay_i_0_ (|command:command1|command_delay_i0)
- 2 - A 10 DFFE + ! 0 2 0 1 |command:command1|command_delay_i_1_ (|command:command1|command_delay_i1)
- 8 - A 10 DFFE + ! 0 2 0 1 |command:command1|command_delay_i_2_ (|command:command1|command_delay_i2)
- 7 - A 10 DFFE + ! 0 2 0 1 |command:command1|command_delay_i_3_ (|command:command1|command_delay_i3)
- 6 - A 10 DFFE + ! 0 2 0 1 |command:command1|command_delay_i_4_ (|command:command1|command_delay_i4)
- 5 - A 10 DFFE + ! 0 2 0 1 |command:command1|command_delay_i_5_ (|command:command1|command_delay_i5)
- 4 - A 10 DFFE + ! 0 2 0 1 |command:command1|command_delay_i_6_ (|command:command1|command_delay_i6)
- 3 - A 10 DFFE + ! 0 1 0 1 |command:command1|command_delay_i_7_ (|command:command1|command_delay_i7)
- 4 - A 12 DFFE + 1 3 0 1 |command:command1|CS_N_0_ (|command:command1|CS_N2)
- 5 - A 12 DFFE + 1 3 0 1 |command:command1|CS_N_1_ (|command:command1|CS_N3)
- 1 - E 10 CASCADE 0 2 0 1 |command:command1|N_8 (|command:command1|do_refresh13_0_and2_cas)
- 3 - E 10 DFFE + 0 4 0 13 |command:command1|do_writea1_1
- 2 - A 12 AND2 0 4 0 3 |command:command1|N_5 (|command:command1|G_104_cand)
- 3 - E 03 OR2 0 2 0 2 |command:command1|G_107~2
- 5 - A 02 AND2 0 2 0 4 |command:command1|G_131~1
- 1 - A 13 LCELL 0 2 0 13 |command:command1|G_134 (|command:command1|G_134_lc)
- 1 - A 12 LCELL 0 2 0 4 |command:command1|G_136 (|command:command1|G_136_lc)
- 1 - E 04 AND2 0 3 0 1 |command:command1|G_147~2
- 6 - A 01 OR2 0 4 0 1 |command:command1|G_161~8
- 5 - E 03 OR2 ! 0 3 0 1 |command:command1|G_164~2
- 8 - E 08 OR2 0 3 0 1 |command:command1|G_173~5
- 8 - E 09 DFFE + 0 4 0 1 |command:command1|oe_shift_0_ (|command:command1|oe_shift7)
- 7 - E 09 DFFE + 0 4 0 1 |command:command1|oe_shift_1_ (|command:command1|oe_shift8)
- 6 - E 09 DFFE + 0 4 0 1 |command:command1|oe_shift_2_ (|command:command1|oe_shift9)
- 5 - E 09 DFFE + 0 4 0 1 |command:command1|oe_shift_3_ (|command:command1|oe_shift10)
- 3 - E 09 DFFE + 0 4 0 1 |command:command1|oe_shift_4_ (|command:command1|oe_shift11)
- 2 - E 09 DFFE + 0 4 0 1 |command:command1|oe_shift_5_ (|command:command1|oe_shift12)
- 1 - E 09 DFFE + 0 3 0 1 |command:command1|oe_shift_6_ (|command:command1|oe_shift13)
- 1 - E 03 DFFE + 0 4 0 0 |command:command1|OE4
- 6 - A 13 DFFE + 1 2 0 1 |command:command1|RAS_N1
- 8 - A 13 OR2 0 4 0 1 |command:command1|RAS_N_13_0_and2~6
- 7 - E 13 DFFE + 0 2 0 1 |command:command1|REF_ACK1
- 7 - A 02 DFFE + ! 0 3 0 1 |command:command1|rp_shift_i_0_ (|command:command1|rp_shift_i0)
- 6 - A 02 DFFE + ! 0 3 0 1 |command:command1|rp_shift_i_1_ (|command:command1|rp_shift_i1)
- 4 - A 02 DFFE + ! 0 3 0 1 |command:command1|rp_shift_i_2_ (|command:command1|rp_shift_i2)
- 3 - A 02 DFFE + 0 2 0 1 |command:command1|rp_shift_3_ (|command:command1|rp_shift3)
- 8 - E 04 DFFE + 0 4 0 1 |command:command1|rw_shift_0_ (|command:command1|rw_shift0)
- 7 - E 04 DFFE + 0 4 0 1 |command:command1|rw_shift_1_ (|command:command1|rw_shift1)
- 2 - A 06 CASCADE 1 3 0 1 |command:command1|N_6 (|command:command1|SA_12_i_cas_10_)
- 6 - E 05 DFFE + 1 3 0 1 |command:command1|SA_0_ (|command:command1|SA12)
- 6 - E 06 DFFE + 1 3 0 1 |command:command1|SA_1_ (|command:command1|SA13)
- 7 - E 06 DFFE + 1 3 0 1 |command:command1|SA_2_ (|command:command1|SA14)
- 6 - E 07 DFFE + 1 3 0 1 |command:command1|SA_3_ (|command:command1|SA15)
- 6 - E 18 DFFE + 1 3 0 1 |command:command1|SA_4_ (|command:command1|SA16)
- 8 - E 15 DFFE + 1 3 0 1 |command:command1|SA_5_ (|command:command1|SA17)
- 7 - E 21 DFFE + 1 3 0 1 |command:command1|SA_6_ (|command:command1|SA18)
- 8 - E 21 DFFE + 1 3 0 1 |command:command1|SA_7_ (|command:command1|SA19)
- 6 - E 02 DFFE + 1 3 0 1 |command:command1|SA_8_ (|command:command1|SA20)
- 7 - E 17 DFFE + 1 3 0 1 |command:command1|SA_9_ (|command:command1|SA21)
- 3 - A 06 DFFE + 0 5 0 1 |command:command1|SA_10_ (|command:command1|SA22)
- 5 - A 06 DFFE + 1 3 0 1 |command:command1|SA_11_ (|command:command1|SA23)
- 6 - E 04 OR2 0 3 0 2 |command:command1|un1_do_rw21_2_i~6
- 5 - E 04 OR2 0 4 0 1 |command:command1|un1_do_rw21_7_i~8
- 6 - E 03 OR2 0 4 0 1 |command:command1|un1_un1_un1_SC_PM_0~8
- 7 - A 13 DFFE + 1 3 0 1 |command:command1|WE_N1
- 4 - E 03 DFFE + 0 4 0 2 |command:command1|oe4_i (|command:command1|:95)
- 2 - E 04 DFFE + ! 0 3 0 4 |command:command1|do_rw_i (|command:command1|:97)
- 2 - A 02 DFFE + ! 0 2 0 8 |command:command1|command_done_i (|command:command1|:98)
- 8 - A 02 DFFE + ! 0 3 0 1 |command:command1|rp_done_i (|command:command1|:99)
- 2 - A 01 DFFE + 0 2 0 4 |command:command1|do_load_mode (|command:command1|:101)
- 1 - A 01 DFFE + 0 2 0 8 |command:command1|do_precharge (|command:command1|:102)
- 6 - E 10 DFFE + 0 3 0 11 |command:command1|do_reada (|command:command1|:104)
- 4 - E 10 DFFE + 0 3 0 10 |command:command1|do_writea (|command:command1|:105)
- 8 - E 03 DFFE + 0 2 0 2 |command:command1|oe3 (|command:command1|:106)
- 7 - E 03 DFFE + 0 2 0 1 |command:command1|oe2 (|command:command1|:107)
- 2 - E 10 DFFE + 0 4 0 11 |command:command1|do_refresh (|command:command1|:108)
- 5 - A 13 DFFE + 0 2 0 2 |command:command1|rw_flag (|command:command1|:109)
- 4 - E 09 DFFE + 0 3 0 1 |command:command1|oe1 (|command:command1|:110)
- 2 - E 03 LCELL 0 2 0 3 |command:command1|G_105 (|command:command1|:142)
- 4 - E 08 LCELL 0 4 0 7 |command:command1|un1_SC_PM_6_i (|command:command1|:143)
- 7 - E 08 LCELL 0 4 0 1 |command:command1|un1_SC_PM_6_i_and2 (|command:command1|:144)
- 2 - A 13 LCELL 1 4 0 1 |command:command1|WE_N_13_0_iv_0_and2_0 (|command:command1|:148)
- 3 - A 13 SOFT s ! 0 1 0 1 |command:command1|G_104~1 (|command:command1|~151~1)
- 1 - A 10 LCELL 0 1 0 11 |command:command1|G_104 (|command:command1|:151)
- 6 - E 17 DFFE + 0 3 1 2 |control_interface:control1|CMD_ACK
- 5 - E 08 OR2 0 4 0 16 |control_interface:control1|G_1_i_and2_0_and2~9
- 4 - E 32 AND2 2 1 0 1 |control_interface:control1|G_158~2
- 4 - E 36 AND2 2 1 0 1 |control_interface:control1|G_159~2
- 5 - A 01 DFFE + 3 0 0 1 |control_interface:control1|LOAD_MODE1
- 4 - A 01 DFFE + 3 0 0 1 |control_interface:control1|PRECHARGE1
- 5 - E 10 DFFE + 3 0 0 1 |control_interface:control1|READA1
- 2 - E 05 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_0_ (|control_interface:control1|REF_PER0)
- 5 - E 06 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_1_ (|control_interface:control1|REF_PER1)
- 5 - E 15 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_2_ (|control_interface:control1|REF_PER2)
- 2 - E 07 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_3_ (|control_interface:control1|REF_PER3)
- 2 - E 18 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_4_ (|control_interface:control1|REF_PER4)
- 2 - E 15 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_5_ (|control_interface:control1|REF_PER5)
- 1 - E 21 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_6_ (|control_interface:control1|REF_PER6)
- 2 - E 21 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_7_ (|control_interface:control1|REF_PER7)
- 1 - E 02 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_8_ (|control_interface:control1|REF_PER8)
- 3 - E 05 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_9_ (|control_interface:control1|REF_PER9)
- 1 - E 06 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_10_ (|control_interface:control1|REF_PER10)
- 1 - E 11 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_11_ (|control_interface:control1|REF_PER11)
- 3 - E 07 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_12_ (|control_interface:control1|REF_PER12)
- 3 - E 18 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_13_ (|control_interface:control1|REF_PER13)
- 3 - E 15 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_14_ (|control_interface:control1|REF_PER14)
- 1 - E 35 DFFE + 0 2 0 1 |control_interface:control1|REF_PER_15_ (|control_interface:control1|REF_PER15)
- 4 - E 17 SOFT s ! 0 1 0 16 |control_interface:control1|REF_REQ1~1
- 5 - E 13 DFFE + 0 2 0 8 |control_interface:control1|REF_REQ1
- 8 - E 10 DFFE + 3 0 0 1 |control_interface:control1|REFRESH1
- 4 - E 05 DFFE + 1 0 0 2 |control_interface:control1|SADDR_0_ (|control_interface:control1|SADDR23)
- 4 - E 06 DFFE + 1 0 0 2 |control_interface:control1|SADDR_1_ (|control_interface:control1|SADDR24)
- 1 - E 15 DFFE + 1 0 0 3 |control_interface:control1|SADDR_2_ (|control_interface:control1|SADDR25)
- 4 - E 07 DFFE + 1 0 0 3 |control_interface:control1|SADDR_3_ (|control_interface:control1|SADDR26)
- 4 - E 18 DFFE + 1 0 0 2 |control_interface:control1|SADDR_4_ (|control_interface:control1|SADDR27)
- 6 - E 15 DFFE + 1 0 0 2 |control_interface:control1|SADDR_5_ (|control_interface:control1|SADDR28)
- 4 - E 21 DFFE + 1 0 0 2 |control_interface:control1|SADDR_6_ (|control_interface:control1|SADDR29)
- 5 - E 21 DFFE + 1 0 0 2 |control_interface:control1|SADDR_7_ (|control_interface:control1|SADDR30)
- 4 - E 02 DFFE + 1 0 0 3 |control_interface:control1|SADDR_8_ (|control_interface:control1|SADDR31)
- 5 - E 05 DFFE + 1 0 0 3 |control_interface:control1|SADDR_9_ (|control_interface:control1|SADDR32)
- 2 - E 06 DFFE + 1 0 0 3 |control_interface:control1|SADDR_10_ (|control_interface:control1|SADDR33)
- 3 - E 11 DFFE + 1 0 0 3 |control_interface:control1|SADDR_11_ (|control_interface:control1|SADDR34)
- 5 - E 07 DFFE + 1 0 0 3 |control_interface:control1|SADDR_12_ (|control_interface:control1|SADDR35)
- 5 - E 18 DFFE + 1 0 0 2 |control_interface:control1|SADDR_13_ (|control_interface:control1|SADDR36)
- 7 - E 15 DFFE + 1 0 0 2 |control_interface:control1|SADDR_14_ (|control_interface:control1|SADDR37)
- 2 - E 35 DFFE + 1 0 0 2 |control_interface:control1|SADDR_15_ (|control_interface:control1|SADDR38)
- 1 - E 23 DFFE + 1 0 0 1 |control_interface:control1|SADDR_16_ (|control_interface:control1|SADDR39)
- 5 - E 02 DFFE + 1 0 0 1 |control_interface:control1|SADDR_17_ (|control_interface:control1|SADDR40)
- 5 - E 17 DFFE + 1 0 0 1 |control_interface:control1|SADDR_18_ (|control_interface:control1|SADDR41)
- 8 - A 06 DFFE + 1 0 0 1 |control_interface:control1|SADDR_19_ (|control_interface:control1|SADDR42)
- 4 - A 06 DFFE + 1 0 0 2 |control_interface:control1|SADDR_20_ (|control_interface:control1|SADDR43)
- 1 - A 17 DFFE + 1 0 0 1 |control_interface:control1|SADDR_21_ (|control_interface:control1|SADDR44)
- 3 - A 12 DFFE + 1 0 0 2 |control_interface:control1|SADDR_22_ (|control_interface:control1|SADDR45)
- 1 - E 05 DFFE + 0 2 0 5 |control_interface:control1|SC_BL_0_ (|control_interface:control1|SC_BL4)
- 6 - E 08 DFFE + 0 2 0 4 |control_interface:control1|SC_BL_1_ (|control_interface:control1|SC_BL5)
- 2 - E 11 DFFE + 0 2 0 3 |control_interface:control1|SC_BL_2_ (|control_interface:control1|SC_BL6)
- 1 - E 07 DFFE + 0 2 0 3 |control_interface:control1|SC_BL_3_ (|control_interface:control1|SC_BL7)
- 2 - E 02 SOFT s ! 0 1 0 1 |control_interface:control1|SC_PM1~1
- 3 - E 02 DFFE + 0 2 0 9 |control_interface:control1|SC_PM1
- 3 - E 04 DFFE + 0 2 0 4 |control_interface:control1|SC_RC_0_ (|control_interface:control1|SC_RC2)
- 4 - E 04 DFFE + 0 2 0 3 |control_interface:control1|SC_RC_1_ (|control_interface:control1|SC_RC3)
- 1 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_0_ (|control_interface:control1|timer0)
- 2 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_1_ (|control_interface:control1|timer1)
- 3 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_2_ (|control_interface:control1|timer2)
- 4 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_3_ (|control_interface:control1|timer3)
- 5 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_4_ (|control_interface:control1|timer4)
- 6 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_5_ (|control_interface:control1|timer5)
- 7 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_6_ (|control_interface:control1|timer6)
- 8 - E 14 DFFE + 0 3 0 1 |control_interface:control1|timer_7_ (|control_interface:control1|timer7)
- 1 - E 16 DFFE + 0 3 0 1 |control_interface:control1|timer_8_ (|control_interface:control1|timer8)
- 2 - E 16 DFFE + 0 3 0 1 |control_interface:control1|timer_9_ (|control_interface:control1|timer9)
- 3 - E 16 DFFE + 0 3 0 1 |control_interface:control1|timer_10_ (|control_in⌨️ 快捷键说明
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