📄 sdr_sdram.rpt
字号:
|control_interface:control1|l2_9:timer_c14_L|
|control_interface:control1|l2_9:timer_c14_L|21mux:G_2|
|control_interface:control1|l2_e:timer_c14_C|
|control_interface:control1|l2_e:timer_c14_C|s_or2:G_1|
|control_interface:control1|l2_9:timer_c15_L|
|control_interface:control1|l2_9:timer_c15_L|21mux:G_2|
|command:command1|
|command:command1|l2_1:G_105_L|
|command:command1|l4_fff8:un1_SC_PM_6_i_L|
|command:command1|l4_fff8:un1_SC_PM_6_i_L|s_or2:G_2|
|command:command1|l4_fff8:un1_SC_PM_6_i_L|s_or2:G_3|
|command:command1|l4_60:un1_SC_PM_6_i_and2_L|
|command:command1|l4_60:un1_SC_PM_6_i_and2_L|21mux:G_3|
|sdr_data_path:data_path1|
|l2_1:I_115_L|
Device-Specific Information: g:\hdl_doc\ip\sdram\source\rev_1\sdr_sdram.rpt
sdr_sdram
***** Logic for device 'sdr_sdram' compiled without errors.
Device: EP1K30FC256-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
Device-Specific Information: g:\hdl_doc\ip\sdram\source\rev_1\sdr_sdram.rpt
sdr_sdram
** ERROR SUMMARY **
Info: Chip 'sdr_sdram' in device 'EP1K30FC256-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
----------------------------------------------------
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 |
|T o o o o o o o o o o o o o o o o T|
|R o o o o o o o o o o o o o o o o R|
|P o o o o o o o o o o o o o o o o P|
|N o o o o o o o o o o o o o o o o N|
|M o o o o o o o o o o o o o o o o M|
|L o o o o o o o o o o o o o o o o L|
|K o o o o o o o o o o o o o o o o K|
|J o o o o o o o o o o o o o o o o J|
|H o o o o o o o o o o o o o o o o H|
|G o o o o o o o o o o o o o o o o G|
|F o o o o o o o o o o o o o o o o F|
|E o o o o o o o o o o o o o o o o E|
|D o o o o o o o o o o o o o o o o D|
|C o o o o o o o o o o o o o o o o C|
|B o o o o o o o o o o o o o o o o B|
|A o o o o o o o o o o o o o o o o A|
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 |
----------------------------------------------------
EP1K30FC256-1
Bottom View
Device-Specific Information: g:\hdl_doc\ip\sdram\source\rev_1\sdr_sdram.rpt
sdr_sdram
A1 ^DATA0 D5 DATAIN13 G9 GND K13 SA6 P1 ^MSEL0
A2 RESERVED D6 DATAIN15 G10 GND K14 N.C. P2 DQ6
A3 GND D7 DATAIN31 G11 VCCIO K15 ADDR3 P3 ADDR13
A4 DATAOUT19 D8 ADDR11 G12 DQ8 K16 N.C. P4 ADDR10
A5 DATAOUT22 D9 DATAOUT27 G13 DQ2 L1 GND P5 SA3
A6 DATAOUT6 D10 ADDR7 G14 DQ29 L2 N.C. P6 ADDR17
A7 ADDR12 D11 RESERVED G15 DQ18 L3 SA5 P7 DATAIN25
A8 DATAOUT20 D12 VCCIO G16 DATAOUT12 L4 N.C. P8 BA1
A9 CLK D13 DATAOUT31 H1 N.C. L5 VCCINT P9 DM0
A10 DATAIN10 D14 RESERVED H2 DQ19 L6 GND P10 DQM1
A11 RESERVED D15 ADDR19 H3 DQ12 L7 VCCINT P11 RESERVED
A12 DATAOUT5 D16 DQ14 H4 DATAOUT18 L8 ADDR0 P12 DATAIN0
A13 DATAIN2 E1 CS_N0 H5 DQ15 L9 VCC_CKLK P13 RESERVED
A14 GND E2 DQ9 H6 VCCINT L10 VCCIO P14 DATAIN17
A15 DATAIN8 E3 N.C. H7 VCCINT L11 GND P15 #TMS
A16 RESERVED E4 DATAIN20 H8 GND L12 VCCINT P16 ADDR16
B1 ^nCE E5 GND H9 GND L13 ADDR1 R1 ^MSEL1
B2 ^DCLK E6 VCCIO H10 VCCINT L14 DQM3 R2 VCCINT
B3 ADDR9 E7 ADDR22 H11 VCCIO L15 SA2 R3 DATAOUT13
B4 ADDR21 E8 CMD0 H12 DATAOUT26 L16 CMDACK R4 DATAOUT2
B5 DATAIN27 E9 ADDR6 H13 DATAOUT29 M1 DQ3 R5 RESERVED
B6 ADDR4 E10 RESERVED H14 DQ26 M2 SA8 R6 DATAOUT1
B7 ADDR8 E11 VCCINT H15 DQ16 M3 DQ31 R7 DATAIN3
B8 DATAIN11 E12 GND H16 N.C. M4 DQ22 R8 CMD1
B9 RESET_N E13 DQ23 J1 N.C. M5 GND R9 DATAIN30
B10 DATAIN7 E14 DQ0 J2 DATAOUT25 M6 VCCIO R10 DATAOUT3
B11 DATAIN23 E15 DQ17 J3 DATAIN24 M7 DATAOUT21 R11 DATAOUT24
B12 DATAOUT10 E16 N.C. J4 DATAOUT7 M8 DATAIN4 R12 DATAIN14
B13 DATAOUT0 F1 DATAOUT11 J5 DQ4 M9 CMD2 R13 DM3
B14 RESERVED F2 DATAOUT15 J6 VCCIO M10 DATAOUT23 R14 DM1
B15 #TCK F3 BA0 J7 VCCINT M11 VCCINT R15 DATAIN18
B16 ^nCEO F4 SA11 J8 GND M12 GND R16 #TRST
C1 SA10 F5 VCCINT J9 GND M13 DQ1 T1 RESERVED
C2 #TDI F6 GND J10 VCCINT M14 N.C. T2 ADDR5
C3 DATAIN19 F7 VCCINT J11 VCCINT M15 DATAIN6 T3 DATAIN5
C4 SA1 F8 VCCIO J12 DATAOUT30 M16 N.C. T4 SA0
C5 DATAIN9 F9 VCCINT J13 DATAOUT16 N1 DQ27 T5 ADDR20
C6 DATAIN12 F10 VCCIO J14 DQ7 N2 DATAIN1 T6 ADDR2
C7 GND F11 GND J15 DQM0 N3 DATAIN22 T7 ADDR14
C8 DATAOUT4 F12 VCCINT J16 DQ30 N4 ^nCONFIG T8 GND_CKLK
C9 RESERVED F13 CS_N1 K1 DQ25 N5 DATAOUT14 T9 DATAIN26
C10 DATAIN28 F14 DQM2 K2 SA4 N6 ADDR18 T10 SA7
C11 DM2 F15 DATAOUT9 K3 N.C. N7 RESERVED T11 RESERVED
C12 RAS_N F16 DATAOUT8 K4 DQ20 N8 SA9 T12 ADDR15
C13 DATAIN16 G1 DQ13 K5 GND N9 DATAIN29 T13 RESERVED
C14 CKE G2 DQ21 K6 VCCIO N10 RESERVED T14 RESERVED
C15 ^CONF_DONE G3 N.C. K7 GND N11 RESERVED T15 DATAOUT17
C16 #TDO G4 DQ11 K8 VCCIO N12 VCCIO T16 ^nSTATUS
D1 N.C. G5 DQ5 K9 VCCINT N13 DQ28
D2 CAS_N G6 VCCIO K10 GND N14 DATAOUT28
D3 WE_N G7 GND K11 VCCIO N15 N.C.
D4 DATAIN21 G8 VCCIO K12 DQ24 N16 DQ10
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: g:\hdl_doc\ip\sdram\source\rev_1\sdr_sdram.rpt
sdr_sdram
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
A2 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
A6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
A8 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 1/22( 4%)
A12 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
A13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
A17 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 4/22( 18%)
A18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A21 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
A23 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A27 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A28 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
A31 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A33 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
A35 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A36 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
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