sdr_sdram.tlg

IC内核的设计源码！其中包含MP3内核

Selecting top level module sdr_sdram
Synthesizing module control_interface
@W:"g:\hdl_doc\ip\sdram\source\control_interface.v":93:0:93:5|Register LOAD_REG1 with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
@W:"g:\hdl_doc\ip\sdram\source\control_interface.v":93:0:93:5|Register LOAD_REG2 with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
Synthesizing module command
@W:"g:\hdl_doc\ip\sdram\source\command.v":101:32:101:37|No assignment to do_act
@W:"g:\hdl_doc\ip\sdram\source\command.v":220:0:220:5|Ignoring missing reset value for signal oe4. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\command.v":220:0:220:5|Ignoring missing reset value for signal oe3. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\command.v":125:0:125:5|Ignoring missing reset value for signal do_writea1. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\command.v":220:0:220:5|Optimizing register bit oe_shift[7] to a constant 0
@W:"g:\hdl_doc\ip\sdram\source\command.v":281:0:281:5|Optimizing register bit rw_shift[3] to a constant 0
@W:"g:\hdl_doc\ip\sdram\source\command.v":281:0:281:5|Optimizing register bit rw_shift[2] to a constant 0
@W:"g:\hdl_doc\ip\sdram\source\command.v":53:32:53:34|Input NOP is unused
@W:"g:\hdl_doc\ip\sdram\source\command.v":59:32:59:36|Input SC_CL is unused
@W:"g:\hdl_doc\ip\sdram\source\command.v":61:32:61:37|Input SC_RRD is unused
Synthesizing module sdr_data_path
@W:"g:\hdl_doc\ip\sdram\source\sdr_data_path.v":58:0:58:5|Ignoring missing reset value for signal DQM[3:0]. Did you forget the set/reset assignment for this signal?
@W:"g:\hdl_doc\ip\sdram\source\sdr_data_path.v":35:32:35:33|Input OE is unused
Synthesizing module sdr_sdram