test.prj

IC内核的设计源码！其中包含MP3内核

#-- Synplicity, Inc.
#-- Version 6.2.4
#-- Project file g:\hdl_doc\ip\sdram\source\test.prj
#-- Written on Thu Oct 11 00:19:39 2001


#add_file options
add_file -verilog "command.v"
add_file -verilog "control_interface.v"
add_file -verilog "altclklock.v"
add_file -verilog "params.v"
add_file -verilog "pll1.v"
add_file -verilog "sdr_data_path.v"
add_file -verilog "sdr_sdram.v"

#reporting options


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology ACEX1K
set_option -part EP1K10
set_option -package TC100
set_option -speed_grade -1

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 0.000
set_option -domap 1
set_option -cliquing 1
set_option -pipe 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/sdr_sdram.edf"