sdr_sdram.vqm

IC内核的设计源码！其中包含MP3内核

//
// Written by Synplify
// Wed Jul 12 11:11:13 2000
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\projects\altera\lpcores\sdr\release\v1_2\source\control_interface.v "
// file 2 "\d:\projects\altera\lpcores\sdr\release\v1_2\source\params.v "
// file 3 "\d:\projects\altera\lpcores\sdr\release\v1_2\source\sdr_data_path.v "
// file 4 "\d:\projects\altera\lpcores\sdr\release\v1_2\source\command.v "
// file 5 "\d:\projects\altera\lpcores\sdr\release\v1_2\source\pll1.v "
// file 6 "\d:\projects\altera\lpcores\sdr\release\v1_2\source\sdr_sdram.v "

module sdr_data_path (
  DQM_0,
  DQM_1,
  DQM_2,
  DQM_3,
  DQOUT_0,
  DQOUT_1,
  DQOUT_2,
  DQOUT_3,
  DQOUT_4,
  DQOUT_5,
  DQOUT_6,
  DQOUT_7,
  DQOUT_8,
  DQOUT_9,
  DQOUT_10,
  DQOUT_11,
  DQOUT_12,
  DQOUT_13,
  DQOUT_14,
  DQOUT_15,
  DQOUT_16,
  DQOUT_17,
  DQOUT_18,
  DQOUT_19,
  DQOUT_20,
  DQOUT_21,
  DQOUT_22,
  DQOUT_23,
  DQOUT_24,
  DQOUT_25,
  DQOUT_26,
  DQOUT_27,
  DQOUT_28,
  DQOUT_29,
  DQOUT_30,
  DQOUT_31,
  DATAIN_c_0,
  DATAIN_c_1,
  DATAIN_c_2,
  DATAIN_c_3,
  DATAIN_c_4,
  DATAIN_c_5,
  DATAIN_c_6,
  DATAIN_c_7,
  DATAIN_c_8,
  DATAIN_c_9,
  DATAIN_c_10,
  DATAIN_c_11,
  DATAIN_c_12,
  DATAIN_c_13,
  DATAIN_c_14,
  DATAIN_c_15,
  DATAIN_c_16,
  DATAIN_c_17,
  DATAIN_c_18,
  DATAIN_c_19,
  DATAIN_c_20,
  DATAIN_c_21,
  DATAIN_c_22,
  DATAIN_c_23,
  DATAIN_c_24,
  DATAIN_c_25,
  DATAIN_c_26,
  DATAIN_c_27,
  DATAIN_c_28,
  DATAIN_c_29,
  DATAIN_c_30,
  DATAIN_c_31,
  DM_c_0,
  DM_c_1,
  DM_c_2,
  DM_c_3,
  RESET_N_c,
  RESET_N_i,
  CLK133
);
output DQM_0;
output DQM_1;
output DQM_2;
output DQM_3;
output DQOUT_0;
output DQOUT_1;
output DQOUT_2;
output DQOUT_3;
output DQOUT_4;
output DQOUT_5;
output DQOUT_6;
output DQOUT_7;
output DQOUT_8;
output DQOUT_9;
output DQOUT_10;
output DQOUT_11;
output DQOUT_12;
output DQOUT_13;
output DQOUT_14;
output DQOUT_15;
output DQOUT_16;
output DQOUT_17;
output DQOUT_18;
output DQOUT_19;
output DQOUT_20;
output DQOUT_21;
output DQOUT_22;
output DQOUT_23;
output DQOUT_24;
output DQOUT_25;
output DQOUT_26;
output DQOUT_27;
output DQOUT_28;
output DQOUT_29;
output DQOUT_30;
output DQOUT_31;
input DATAIN_c_0;
input DATAIN_c_1;
input DATAIN_c_2;
input DATAIN_c_3;
input DATAIN_c_4;
input DATAIN_c_5;
input DATAIN_c_6;
input DATAIN_c_7;
input DATAIN_c_8;
input DATAIN_c_9;
input DATAIN_c_10;
input DATAIN_c_11;
input DATAIN_c_12;
input DATAIN_c_13;
input DATAIN_c_14;
input DATAIN_c_15;
input DATAIN_c_16;
input DATAIN_c_17;
input DATAIN_c_18;
input DATAIN_c_19;
input DATAIN_c_20;
input DATAIN_c_21;
input DATAIN_c_22;
input DATAIN_c_23;
input DATAIN_c_24;
input DATAIN_c_25;
input DATAIN_c_26;
input DATAIN_c_27;
input DATAIN_c_28;
input DATAIN_c_29;
input DATAIN_c_30;
input DATAIN_c_31;
input DM_c_0;
input DM_c_1;
input DM_c_2;
input DM_c_3;
input RESET_N_c;
input RESET_N_i;
input CLK133;
wire DQM_0 ;
wire DQM_1 ;
wire DQM_2 ;
wire DQM_3 ;
wire DQOUT_0 ;
wire DQOUT_1 ;
wire DQOUT_2 ;
wire DQOUT_3 ;
wire DQOUT_4 ;
wire DQOUT_5 ;
wire DQOUT_6 ;
wire DQOUT_7 ;
wire DQOUT_8 ;
wire DQOUT_9 ;
wire DQOUT_10 ;
wire DQOUT_11 ;
wire DQOUT_12 ;
wire DQOUT_13 ;
wire DQOUT_14 ;
wire DQOUT_15 ;
wire DQOUT_16 ;
wire DQOUT_17 ;
wire DQOUT_18 ;
wire DQOUT_19 ;
wire DQOUT_20 ;
wire DQOUT_21 ;
wire DQOUT_22 ;
wire DQOUT_23 ;
wire DQOUT_24 ;
wire DQOUT_25 ;
wire DQOUT_26 ;
wire DQOUT_27 ;
wire DQOUT_28 ;
wire DQOUT_29 ;
wire DQOUT_30 ;
wire DQOUT_31 ;
wire DATAIN_c_0 ;
wire DATAIN_c_1 ;
wire DATAIN_c_2 ;
wire DATAIN_c_3 ;
wire DATAIN_c_4 ;
wire DATAIN_c_5 ;
wire DATAIN_c_6 ;
wire DATAIN_c_7 ;
wire DATAIN_c_8 ;
wire DATAIN_c_9 ;
wire DATAIN_c_10 ;
wire DATAIN_c_11 ;
wire DATAIN_c_12 ;
wire DATAIN_c_13 ;
wire DATAIN_c_14 ;
wire DATAIN_c_15 ;
wire DATAIN_c_16 ;
wire DATAIN_c_17 ;
wire DATAIN_c_18 ;
wire DATAIN_c_19 ;
wire DATAIN_c_20 ;
wire DATAIN_c_21 ;
wire DATAIN_c_22 ;
wire DATAIN_c_23 ;
wire DATAIN_c_24 ;
wire DATAIN_c_25 ;
wire DATAIN_c_26 ;
wire DATAIN_c_27 ;
wire DATAIN_c_28 ;
wire DATAIN_c_29 ;
wire DATAIN_c_30 ;
wire DATAIN_c_31 ;
wire DM_c_0 ;
wire DM_c_1 ;
wire DM_c_2 ;
wire DM_c_3 ;
wire RESET_N_c ;
wire RESET_N_i ;
wire CLK133 ;
wire [3:0] DM_c;
wire [31:0] DATAIN_c;
wire [31:0] DQOUT;
wire [31:0] DIN1;
wire [3:0] DQM;
wire [3:0] DM1;
wire GND ;
wire VCC ;
//@4:158
  assign VCC = 1'b1;
//@4:158
  assign GND = 1'b0;
// @3:69
  apex20ke_lcell DQM_0_ (
	.regout(DQM[0]),
	.clk(CLK133),
	.dataa(DM1[0]),
	.ena(RESET_N_c)
);
defparam DQM_0_.operation_mode="normal";
defparam DQM_0_.output_mode="reg_only";
defparam DQM_0_.packed_mode="false";
defparam DQM_0_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQM_1_ (
	.regout(DQM[1]),
	.clk(CLK133),
	.dataa(DM1[1]),
	.ena(RESET_N_c)
);
defparam DQM_1_.operation_mode="normal";
defparam DQM_1_.output_mode="reg_only";
defparam DQM_1_.packed_mode="false";
defparam DQM_1_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQM_2_ (
	.regout(DQM[2]),
	.clk(CLK133),
	.dataa(DM1[2]),
	.ena(RESET_N_c)
);
defparam DQM_2_.operation_mode="normal";
defparam DQM_2_.output_mode="reg_only";
defparam DQM_2_.packed_mode="false";
defparam DQM_2_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQM_3_ (
	.regout(DQM[3]),
	.clk(CLK133),
	.dataa(DM1[3]),
	.ena(RESET_N_c)
);
defparam DQM_3_.operation_mode="normal";
defparam DQM_3_.output_mode="reg_only";
defparam DQM_3_.packed_mode="false";
defparam DQM_3_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_0_ (
	.regout(DQOUT[0]),
	.clk(CLK133),
	.dataa(DIN1[0]),
	.aclr(RESET_N_i)
);
defparam DQOUT_0_.operation_mode="normal";
defparam DQOUT_0_.output_mode="reg_only";
defparam DQOUT_0_.packed_mode="false";
defparam DQOUT_0_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_1_ (
	.regout(DQOUT[1]),
	.clk(CLK133),
	.dataa(DIN1[1]),
	.aclr(RESET_N_i)
);
defparam DQOUT_1_.operation_mode="normal";
defparam DQOUT_1_.output_mode="reg_only";
defparam DQOUT_1_.packed_mode="false";
defparam DQOUT_1_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_2_ (
	.regout(DQOUT[2]),
	.clk(CLK133),
	.dataa(DIN1[2]),
	.aclr(RESET_N_i)
);
defparam DQOUT_2_.operation_mode="normal";
defparam DQOUT_2_.output_mode="reg_only";
defparam DQOUT_2_.packed_mode="false";
defparam DQOUT_2_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_3_ (
	.regout(DQOUT[3]),
	.clk(CLK133),
	.dataa(DIN1[3]),
	.aclr(RESET_N_i)
);
defparam DQOUT_3_.operation_mode="normal";
defparam DQOUT_3_.output_mode="reg_only";
defparam DQOUT_3_.packed_mode="false";
defparam DQOUT_3_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_4_ (
	.regout(DQOUT[4]),
	.clk(CLK133),
	.dataa(DIN1[4]),
	.aclr(RESET_N_i)
);
defparam DQOUT_4_.operation_mode="normal";
defparam DQOUT_4_.output_mode="reg_only";
defparam DQOUT_4_.packed_mode="false";
defparam DQOUT_4_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_5_ (
	.regout(DQOUT[5]),
	.clk(CLK133),
	.dataa(DIN1[5]),
	.aclr(RESET_N_i)
);
defparam DQOUT_5_.operation_mode="normal";
defparam DQOUT_5_.output_mode="reg_only";
defparam DQOUT_5_.packed_mode="false";
defparam DQOUT_5_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_6_ (
	.regout(DQOUT[6]),
	.clk(CLK133),
	.dataa(DIN1[6]),
	.aclr(RESET_N_i)
);
defparam DQOUT_6_.operation_mode="normal";
defparam DQOUT_6_.output_mode="reg_only";
defparam DQOUT_6_.packed_mode="false";
defparam DQOUT_6_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_7_ (
	.regout(DQOUT[7]),
	.clk(CLK133),
	.dataa(DIN1[7]),
	.aclr(RESET_N_i)
);
defparam DQOUT_7_.operation_mode="normal";
defparam DQOUT_7_.output_mode="reg_only";
defparam DQOUT_7_.packed_mode="false";
defparam DQOUT_7_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_8_ (
	.regout(DQOUT[8]),
	.clk(CLK133),
	.dataa(DIN1[8]),
	.aclr(RESET_N_i)
);
defparam DQOUT_8_.operation_mode="normal";
defparam DQOUT_8_.output_mode="reg_only";
defparam DQOUT_8_.packed_mode="false";
defparam DQOUT_8_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_9_ (
	.regout(DQOUT[9]),
	.clk(CLK133),
	.dataa(DIN1[9]),
	.aclr(RESET_N_i)
);
defparam DQOUT_9_.operation_mode="normal";
defparam DQOUT_9_.output_mode="reg_only";
defparam DQOUT_9_.packed_mode="false";
defparam DQOUT_9_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_10_ (
	.regout(DQOUT[10]),
	.clk(CLK133),
	.dataa(DIN1[10]),
	.aclr(RESET_N_i)
);
defparam DQOUT_10_.operation_mode="normal";
defparam DQOUT_10_.output_mode="reg_only";
defparam DQOUT_10_.packed_mode="false";
defparam DQOUT_10_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_11_ (
	.regout(DQOUT[11]),
	.clk(CLK133),
	.dataa(DIN1[11]),
	.aclr(RESET_N_i)
);
defparam DQOUT_11_.operation_mode="normal";
defparam DQOUT_11_.output_mode="reg_only";
defparam DQOUT_11_.packed_mode="false";
defparam DQOUT_11_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_12_ (
	.regout(DQOUT[12]),
	.clk(CLK133),
	.dataa(DIN1[12]),
	.aclr(RESET_N_i)
);
defparam DQOUT_12_.operation_mode="normal";
defparam DQOUT_12_.output_mode="reg_only";
defparam DQOUT_12_.packed_mode="false";
defparam DQOUT_12_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_13_ (
	.regout(DQOUT[13]),
	.clk(CLK133),
	.dataa(DIN1[13]),
	.aclr(RESET_N_i)
);
defparam DQOUT_13_.operation_mode="normal";
defparam DQOUT_13_.output_mode="reg_only";
defparam DQOUT_13_.packed_mode="false";
defparam DQOUT_13_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_14_ (
	.regout(DQOUT[14]),
	.clk(CLK133),
	.dataa(DIN1[14]),
	.aclr(RESET_N_i)
);
defparam DQOUT_14_.operation_mode="normal";
defparam DQOUT_14_.output_mode="reg_only";
defparam DQOUT_14_.packed_mode="false";
defparam DQOUT_14_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_15_ (
	.regout(DQOUT[15]),
	.clk(CLK133),
	.dataa(DIN1[15]),
	.aclr(RESET_N_i)
);
defparam DQOUT_15_.operation_mode="normal";
defparam DQOUT_15_.output_mode="reg_only";
defparam DQOUT_15_.packed_mode="false";
defparam DQOUT_15_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_16_ (
	.regout(DQOUT[16]),
	.clk(CLK133),
	.dataa(DIN1[16]),
	.aclr(RESET_N_i)
);
defparam DQOUT_16_.operation_mode="normal";
defparam DQOUT_16_.output_mode="reg_only";
defparam DQOUT_16_.packed_mode="false";
defparam DQOUT_16_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_17_ (
	.regout(DQOUT[17]),
	.clk(CLK133),
	.dataa(DIN1[17]),
	.aclr(RESET_N_i)
);
defparam DQOUT_17_.operation_mode="normal";
defparam DQOUT_17_.output_mode="reg_only";
defparam DQOUT_17_.packed_mode="false";
defparam DQOUT_17_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_18_ (
	.regout(DQOUT[18]),
	.clk(CLK133),
	.dataa(DIN1[18]),
	.aclr(RESET_N_i)
);
defparam DQOUT_18_.operation_mode="normal";
defparam DQOUT_18_.output_mode="reg_only";
defparam DQOUT_18_.packed_mode="false";
defparam DQOUT_18_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_19_ (
	.regout(DQOUT[19]),
	.clk(CLK133),
	.dataa(DIN1[19]),
	.aclr(RESET_N_i)
);
defparam DQOUT_19_.operation_mode="normal";
defparam DQOUT_19_.output_mode="reg_only";
defparam DQOUT_19_.packed_mode="false";
defparam DQOUT_19_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_20_ (
	.regout(DQOUT[20]),
	.clk(CLK133),
	.dataa(DIN1[20]),
	.aclr(RESET_N_i)
);
defparam DQOUT_20_.operation_mode="normal";
defparam DQOUT_20_.output_mode="reg_only";
defparam DQOUT_20_.packed_mode="false";
defparam DQOUT_20_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_21_ (
	.regout(DQOUT[21]),
	.clk(CLK133),
	.dataa(DIN1[21]),
	.aclr(RESET_N_i)
);
defparam DQOUT_21_.operation_mode="normal";
defparam DQOUT_21_.output_mode="reg_only";
defparam DQOUT_21_.packed_mode="false";
defparam DQOUT_21_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_22_ (
	.regout(DQOUT[22]),
	.clk(CLK133),
	.dataa(DIN1[22]),
	.aclr(RESET_N_i)
);
defparam DQOUT_22_.operation_mode="normal";
defparam DQOUT_22_.output_mode="reg_only";
defparam DQOUT_22_.packed_mode="false";
defparam DQOUT_22_.lut_mask="aaaa";
// @3:69
  apex20ke_lcell DQOUT_23_ (