dc_top.tcl

synopsys dc_shell 用户手册

#     -gate_clock
#     -retime
#     -timing_high_effort_script
#     -area_high_effort_script
#     -congestion
#
# Use compile_ultra as your starting point. For test-ready compile, include
# the -scan option with the first compile and any subsequent compiles.
#
# Use -gate_clock to insert clock-gating logic during optimization.  This
# is now the recommended methodology for clock gating.
#
# Use -retime to enable adapative retiming optimization for further timing
# benefit without any runtime or memory overhead.
#
# The -timing_high_effort_script or the -area_high_effort_script option
# may also be used to try and improve the optimization results at the tradeoff
# of some additional runtime.
#
# The -congestion option (topographical mode only) enables specialized optimizations that
# reduce routing related congestion during synthesis.
# This option requires a license for DC Graphical.
#
#################################################################################

# Before running topographical mode synthesis for the first time, run
# "compile_ultra -check_only" to verify that your libraries and design
# will not fail during optimization in topographical mode.

# compile_ultra -check_only
# quit

# Clock gating is now recommended with -gate_clock instead of using insert_clock_gating
compile_ultra -scan -gate_clock

#################################################################################
# Save Design after First Compile
#################################################################################

write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.compile_ultra.ddc

#################################################################################
# DFT Compiler Optimization Section
#################################################################################

    #############################################################################
    # DFT Signal Type Definitions
    #
    # These are design-specific settings that should be modified.
    # The following are only examples and should not be used.
    #############################################################################

    # It is recommended that top-level test ports be defined as a part of the
    # RTL design and included in the netlist for floorplanning.

    # If you create test ports here and they are not in your floorplan, you will
    # need to set_port_location for these additional test ports when
    # performing placement in ICC.  For better correlation also include these
    # port locations for topographical mode synthesis.

    # create_port ScanPortName ... (repeat for each new test port)

    if {[shell_is_in_topographical_mode]} {
      # set_port_location -coordinate {x y} ScanPortName ... (repeat for each new test port)
    }

    set_dft_signal -type ScanDataOut -port SO -view spec
    set_dft_signal -type ScanDataIn -port SI -view spec
    set_dft_signal -type ScanEnable -port SCAN_ENABLE  -view spec
    set_dft_signal -view existing_dft -type ScanClock -timing {45 55} -port [list CLK]
    set_dft_signal -view existing_dft -type Reset -port RESET -active 0

    # Define the test-mode signal to be used for hookup_testports.
    # Do not define other test-mode signals (eg. for ADAPTIVE SCAN)
    set_dft_signal -type TestMode -port test_mode  -view spec

    #############################################################################
    # DFT for Clock Gating
    #
    # This section includes variables and commands used only when clock-gating
    # has been performed in the design.
    #############################################################################

    # Modify the following as needed to initialize clock gating cells for test
    set_dft_drc_configuration -clock_gating_init_cycles 1 

    # Note: hookup_testports functionality will be fully integrated into insert_dft
    #       by B-2008.09-SP1.  We will be recommending that you remove hookup_testports
    #       from your scripts.  Look for this recommended change in the next DC-RM release.

    hookup_testports -verbose > ${REPORTS_DIR}/${DESIGN_NAME}.hookup_testports.log
    
    #############################################################################
    # DFT Configuration
    #############################################################################

    set_dft_insertion_configuration -preserve_design_name true

    # Do not run incremental compile as a part of insert_dft
    set_dft_insertion_configuration -synthesis_optimization none

    ## DFT Clock Mixing Specification
    # For top-level integration clock mixing is recommended, if possible:
    set_scan_configuration -clock_mixing mix_clocks

    # If clock-mixing is not possible, use the following setting:
    # set_scan_configuration -clock_mixing no_mix
    
    # Use the following to enable ADAPTIVE SCAN
    # set_dft_configuration -scan_compression enable

    # Use the following to define the test-mode to be used for ADAPTIVE SCAN
    # set_dft_signal -type TestMode -view spec -port scan_compression_enable


    # If any hierarchical blocks contain ADAPTIVE SCAN compression, use
    # ONE of the following mutually exclusive settings to specify the integration strategy:

    # If NOT using Adaptive SCAN compression at the top-level:
    # set_scan_compression_configuration -integration_only true
    #                      OR
    # If also adding ADAPTIVE SCAN compression at the top-level:
    # set_scan_compression_configuration -hybrid true

    # Add any additional design-specific DFT constraints here

    # Starting with 2008.09, we recommend the use of"-capture_procedure multi_clock"
    # for the create_test_protocol command. 
    # As early as 2008.09-SP2 release, "-capture_procedure multi_clock" will be default. 
    # If necessary, you can use the "-capture_procedure single_clock" option. 

    create_test_protocol -capture_procedure multi_clock

    #############################################################################
    # DFT Scan Chain Insertion
    #############################################################################

    # Use the -verbose option of dft_drc to assist in debugging if necessary
    
    dft_drc                                > ${REPORTS_DIR}/${DESIGN_NAME}.dft_drc_configured.rpt
    report_scan_configuration              > ${REPORTS_DIR}/${DESIGN_NAME}.scan_config.rpt
    report_dft_insertion_configuration     > ${REPORTS_DIR}/${DESIGN_NAME}.report_dft_insertion_config.preview_dft.rpt

    # Use the -show all option to preview_dft for more detailed report
    preview_dft                            > ${REPORTS_DIR}/${DESIGN_NAME}.preview_dft.rpt
    
    insert_dft
   
    #################################################################################
    # DFT Incremental Compile
    #
    # Only required if scan chain insertion has been performed.
    #################################################################################

    compile_ultra -incremental -scan

#################################################################################
# Write Out Final Design and Reports
#
#        .ddc:   Recommended binary format used for subsequent DC sessions
#    Milkyway:   Recommended binary format for IC Compiler
#        .v  :   Verilog netlist for ASCII flow (Formality, PrimeTime, VCS)
#       .spef:   Topographical mode parasitics for PrimeTime
#        .sdf:   SDF backannotated topographical mode timing for PrimeTime
#        .sdc:   SDC constraints for ASCII flow
#
#################################################################################

change_names -rules verilog -hierarchy

    #############################################################################
    # DFT Write out Test Protocols and Reports
    #############################################################################

    # Write out top-level SCANDEF for physical synthesis
    write_scan_def -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scandef

    # Note: check_scan_def is not supported with subdesign abstraction

    # Write out expanded SCANDEF for floorplanning purposes
    # Need to derive Tcl list of hierarchical cells that are not ICC ILMs for SCANDEF expansion
    set HIER_DESIGNS "${DDC_HIER_DESIGNS} ${DC_ILM_HIER_DESIGNS}"
    if { ${HIER_DESIGNS} != ""} {
      set hier_cells ""
      foreach_in_collection hier_cell [sub_instances_of -hierarchy -of_references ${HIER_DESIGNS} ${DESIGN_NAME}] {
        lappend hier_cells [get_object_name $hier_cell]
      }
      write_scan_def -expand_elements ${hier_cells} -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.expanded.scandef
    }

    # If NOT using ADAPTIVE SCAN
    write_test_protocol -names verilog -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scan.spf
    dft_drc > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.dft_drc_inserted.rpt
    report_scan_path > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.scanpath.rpt

    # OR

    # If using ADAPTIVE SCAN
    # write_test_protocol -test_mode Internal_scan -names verilog -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scan.spf
    # write_test_protocol -test_mode ScanCompression_mode -names verilog -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scancompress.spf
    # current_test_mode Internal_scan
    # dft_drc > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.dft_drc_inserted.rpt
    # current_test_mode ScanCompression_mode
    # Note: dft_drc for ADAPTIVE SCAN is not supported at the top-level
    # report_scan_path > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.scanpath.scan_compression.rpt


    # For BOTH adaptive and non-adaptive scan

    report_dft_signal > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.dft_signals.rpt

#################################################################################
# Write out Design Data
#################################################################################

if {[shell_is_in_topographical_mode]} {

  write_physical_constraints -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.physical_constraints.tcl

  # Write parasitics data from DCT placement for static timing analysis
  write_parasitics -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef

  # Write SDF backannotation data from DCT placement for static timing analysis
  write_sdf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdf

  # Do not write out net RC info into SDC
  set write_sdc_output_lumped_net_capacitance false
  set write_sdc_output_net_resistance false
}

write_sdc -nosplit ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdc

# If SAIF is used, write out SAIF name mapping file for PrimeTime-PX
# saif_map -type ptpx -write_map ${RESULTS_DIR}/${DESIGN_NAME}.mapped.SAIF.namemap


#################################################################################
# Generate Final Reports
#################################################################################

report_qor > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.qor.rpt
report_timing -transition_time -nets -attributes -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.timing.rpt
report_area -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt

if {[shell_is_in_topographical_mode]} {
  # report_congestion (topographical mode only) reports estimated routing related congestion
  # after topographical mode synthesis.
  # This command requires a license for DC Graphical.

  report_congestion > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.congestion.rpt
}

# Use SAIF file for power analysis
# read_saif -auto_map_names -input ${DESIGN_NAME}.saif -instance < DESIGN_INSTANCE > -verbose
report_power -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.power.rpt
report_clock_gating -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.clock_gating.rpt

#################################################################################
# Write out Top-Level Design Without Hierarchical Blocks
#
# When reading the design into other tools, read in all of the mapped
# hierarchical blocks and the mapped top-level design.
#
# For ICC: Replace the block DC ILMs with the complete block mapped netlist.
# For Formality: Verify each block (fm.tcl) and top (fm_top.tcl) separately.
#
#################################################################################

if { ${DDC_HIER_DESIGNS} != ""} {
  remove_design -hierarchy ${DDC_HIER_DESIGNS}
}

if { ${DC_ILM_HIER_DESIGNS} != ""} {
  remove_design -hierarchy ${DC_ILM_HIER_DESIGNS}
}

if { ${ICC_ILM_HIER_DESIGNS} != ""} {
  remove_design -hierarchy ${ICC_ILM_HIER_DESIGNS}
}

# Write and close SVF file
set_svf -off

write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc
write -f verilog -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.v

# Note: Do not write out the MW design partitions for hierarchical flow
# MW design partitioning is done during hierarchical design planning in ICC (ICC-HRM)

exit