dc.tcl

synopsys dc_shell 用户手册

# Before running topographical mode synthesis for the first time, run
# "compile_ultra -check_only" to verify that your libraries and design
# will not fail during optimization in topographical mode.

# compile_ultra -check_only
# quit

# Clock gating is now recommended with -gate_clock instead of using insert_clock_gating
compile_ultra -scan -gate_clock

#################################################################################
# Save Design after First Compile
#################################################################################

write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.compile_ultra.ddc

#################################################################################
# DFT Compiler Optimization Section
#################################################################################

    #############################################################################
    # DFT Signal Type Definitions
    #
    # These are design-specific settings that should be modified.
    # The following are only examples and should not be used.
    #############################################################################

    # It is recommended that top-level test ports be defined as a part of the
    # RTL design and included in the netlist for floorplanning.

    # If you create test ports here and they are not in your floorplan, you will
    # need to set_port_location for these additional test ports when
    # performing placement in ICC.  For better correlation also include these
    # port locations for topographical mode synthesis.

    # create_port ScanPortName ... (repeat for each new test port)

    if {[shell_is_in_topographical_mode]} {
      # set_port_location -coordinate {x y} ScanPortName ... (repeat for each new test port)
    }

    set_dft_signal -type ScanDataOut -port SO -view spec
    set_dft_signal -type ScanDataIn -port SI -view spec
    set_dft_signal -type ScanEnable -port SCAN_ENABLE  -view spec
    set_dft_signal -view existing_dft -type ScanClock -timing {45 55} -port [list CLK]
    set_dft_signal -view existing_dft -type Reset -port RESET -active 0

    # Define the test-mode signal to be used for hookup_testports.
    # Do not define other test-mode signals (eg. for ADAPTIVE SCAN)
    set_dft_signal -type TestMode -port test_mode  -view spec

    #############################################################################
    # DFT for Clock Gating
    #
    # This section includes variables and commands used only when clock-gating
    # has been performed in the design.
    #############################################################################

    # Modify the following as needed to initialize clock gating cells for test
    set_dft_drc_configuration -clock_gating_init_cycles 1 

    # Note: hookup_testports functionality will be fully integrated into insert_dft
    #       by B-2008.09-SP1.  We will be recommending that you remove hookup_testports
    #       from your scripts.  Look for this recommended change in the next DC-RM release.

    hookup_testports -verbose > ${REPORTS_DIR}/${DESIGN_NAME}.hookup_testports.log
    
    #############################################################################
    # DFT Configuration
    #############################################################################

    set_dft_insertion_configuration -preserve_design_name true

    # Do not run incremental compile as a part of insert_dft
    set_dft_insertion_configuration -synthesis_optimization none

    ## DFT Clock Mixing Specification
    # For a hierarchical flow, don't mix clocks at the block-level:
    # set_scan_configuration -clock_mixing no_mix

    # For top-down methodology clock mixing is recommended, if possible:
    set_scan_configuration -clock_mixing mix_clocks

    # Use the following to enable ADAPTIVE SCAN
    # set_dft_configuration -scan_compression enable

    # Use the following to define the test-mode to be used for ADAPTIVE SCAN
    # set_dft_signal -type TestMode -view spec -port scan_compression_enable

    # Add any additional design-specific DFT constraints here

    # Starting with 2008.09, we recommend the use of"-capture_procedure multi_clock"
    # for the create_test_protocol command. 
    # As early as 2008.09-SP2 release, "-capture_procedure multi_clock" will be default. 
    # If necessary, you can use the "-capture_procedure single_clock" option. 

    create_test_protocol -capture_procedure multi_clock

    #############################################################################
    # DFT Scan Chain Insertion
    #############################################################################

    # Use the -verbose option of dft_drc to assist in debugging if necessary
    
    dft_drc                                > ${REPORTS_DIR}/${DESIGN_NAME}.dft_drc_configured.rpt
    report_scan_configuration              > ${REPORTS_DIR}/${DESIGN_NAME}.scan_config.rpt
    report_dft_insertion_configuration     > ${REPORTS_DIR}/${DESIGN_NAME}.report_dft_insertion_config.preview_dft.rpt

    # Use the -show all option to preview_dft for more detailed report
    preview_dft                            > ${REPORTS_DIR}/${DESIGN_NAME}.preview_dft.rpt
    
    insert_dft
   
    #################################################################################
    # DFT Incremental Compile
    #
    # Only required if scan chain insertion has been performed.
    #################################################################################

    compile_ultra -incremental -scan

#################################################################################
# Write Out Final Design and Reports
#
#        .ddc:   Recommended binary format used for subsequent DC sessions
#    Milkyway:   Recommended binary format for IC Compiler
#        .v  :   Verilog netlist for ASCII flow (Formality, PrimeTime, VCS)
#       .spef:   Topographical mode parasitics for PrimeTime
#        .sdf:   SDF backannotated topographical mode timing for PrimeTime
#        .sdc:   SDC constraints for ASCII flow
#
#################################################################################

# If this will be a sub-block in a hierarchical design, uniquify with block unique names
# to avoid name collisions when integrating the design at the top level

# set uniquify_naming_style "${DESIGN_NAME}_%s_%d"
# uniquify -force

change_names -rules verilog -hierarchy

    #############################################################################
    # DFT Write out Test Protocols and Reports
    #############################################################################

    # write_scan_def adds SCANDEF info to the design database in memory so this
    # must be performed prior to writing out the design for binary SCANDEF.

    write_scan_def -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scandef
    check_scan_def > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.check_scan_def.rpt
    write_test_model -format ctl -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ctl

    # If NOT using ADAPTIVE SCAN
    write_test_protocol -names verilog -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scan.spf
    dft_drc > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.dft_drc_inserted.rpt
    report_scan_path > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.scanpath.rpt

    # OR

    # If using ADAPTIVE SCAN
    # write_test_protocol -test_mode Internal_scan -names verilog -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scan.spf
    # write_test_protocol -test_mode ScanCompression_mode -names verilog -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.scancompress.spf
    # current_test_mode Internal_scan
    # dft_drc > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.dft_drc_inserted.rpt
    # current_test_mode ScanCompression_mode
    # dft_drc > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.dft_drc_inserted.scan_compression.rpt
    # report_scan_path > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.scanpath.scan_compression.rpt


    # For BOTH adaptive and non-adaptive scan

    report_dft_signal > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.dft_signals.rpt

#################################################################################
# Write out Design
#################################################################################

# Write and close SVF file and make it available for immediate use
set_svf -off

write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc
write -f verilog -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.v

#################################################################################
# Write out Design Data
#################################################################################

if {[shell_is_in_topographical_mode]} {

  write_physical_constraints -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.physical_constraints.tcl

  # Write parasitics data from DCT placement for static timing analysis
  write_parasitics -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef

  # Write SDF backannotation data from DCT placement for static timing analysis
  write_sdf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdf

  # Do not write out net RC info into SDC
  set write_sdc_output_lumped_net_capacitance false
  set write_sdc_output_net_resistance false
}

write_sdc -nosplit ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdc

# If SAIF is used, write out SAIF name mapping file for PrimeTime-PX
# saif_map -type ptpx -write_map ${RESULTS_DIR}/${DESIGN_NAME}.mapped.SAIF.namemap

#################################################################################
# Generate Final Reports
#################################################################################

report_qor > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.qor.rpt
report_timing -transition_time -nets -attributes -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.timing.rpt
report_area -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt

if {[shell_is_in_topographical_mode]} {
  # report_congestion (topographical mode only) reports estimated routing related congestion
  # after topographical mode synthesis.
  # This command requires a license for DC Graphical.

  report_congestion > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.congestion.rpt
}

# Use SAIF file for power analysis
# read_saif -auto_map_names -input ${DESIGN_NAME}.saif -instance < DESIGN_INSTANCE > -verbose
report_power -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.power.rpt
report_clock_gating -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.clock_gating.rpt

#################################################################################
# Write out MW Design for Top-Down Flow
#
# This should be the last step in the script (for flow stability).
# Do not write out MW if you are using a hierarchical flow and creating
# a DC ILM next.
#################################################################################

if {[shell_is_in_topographical_mode]} {
  # write_milkyway uses: mw_logic1_net, mw_logic0_net and mw_design_library variables from dc_setup.tcl
  write_milkyway -overwrite -output ${DESIGN_NAME}_DCT
}

#################################################################################
# Create DC ILM for Hierarchical Flow
#################################################################################

# If this design will be abstracted as an ILM in a hierarchical flow then
# uncomment the following two lines to create the ILM for this block and comment
# out the write_milkyway step above.

# create_ilm
# write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ILM.ddc

exit