release_notes.dc-rm.txt

synopsys dc_shell 用户手册

############################################################################
# Design Compiler Reference Methodology Release Notes
# Version: B-2008.09 (Oct. 3, 2008)
# Copyright (C) 2007, 2008 Synopsys All rights reserved.
############################################################################

2008.09
=======

* The following new Formality RM scripts have been added:
	dc_scripts/fm_MV.tcl (top-down MultiVoltage Formality script with UPF)
	dc_scripts/fm_top.tcl (top-level Formality script for dc_top.tcl)

* Setup scripts are now sourced verbosely before file header comment block
  to improve logging of script flow.

common_setup.tcl changes:
-------------------------

* Added MW_REFERENCE_CONTROL_FILE variable definition
	-ICC-RM assumes that this variable is defined and can use it
	-DC-RM does not yet make use of this setting

dc_setup.tcl changes:
---------------------

* ICC_ILM_HIER_DESIGNS is commented out temporarily for the hierarchical flow in 2008.09
        ##############################################################################
        # Note: ICC-ILM support is temporarily unavailable in the 2008.09 release due
        # to MW compatibility issues.  There is a plan to fix this in a later
        # service pack.
        ##############################################################################

* set_mw_lib_reference added to the MW library setup
	-Resolves cases where MW reference library changes result in MW design
         library mismatch.


dc_scripts/dc(_MV)(_top).tcl common changes:
--------------------------------------------

* set_max_area 0 removed from the scripts
	-This is the default behavior now for full and incremental compile_ultra

* set_max_total_power power optimization constraint removed from scripts
	-No longer recommended to use this constraint
	-Users can now use all combinations of: set_max_leakage_power and
                                                set_max_dynamic_power

* Removed comment that power prediction does not support ILMs
	-ILMs are now supported with power prediction enabled.

* DFT signal definitions only define TestMode signals for hookup_testports
	-Remaining TestMode signals should be defined after hookup_testports
	-Added separate TestMode signal definition for ADAPTIVE SCAN
	-Recommended also for previous releases

* Note added that hookup_testports functionality has been integrated into
  insert_dft.  Future DC-RM versions will recommend removing hookup_testports
  from the flow.

* Revised DFT clock-mixing specification to clarify differences between block and
  top-level settings in a hierarchical flow.

* create_test_protocol -capture_procedure multi_clock (recommended option)
	-Recommended for ATPG flow
	-This is planned to be the default behavior in 2008.09-SP2

* Added  "-names verilog" to write_test_protocol for regular scan mode
	-Missing in previous RM releases
	-Also recommended for previous releases

* Added "set_svf -off" as recommendation to close and write SVF file
	-Close and make SVF file available earlier in the flow

* report_congestion is now performed by default in the reporting section
	-This command requires a license for DC Graphical


dc_scripts/dc(_MV).tcl common changes:
--------------------------------------

* Reorganized output and reporting sections
	-Output design data early to snapshot and allow parallel analysis
	-Design data is still saved if reporting fails

* write_milkyway moved to the bottom of the script
	-Recommended for stability purposes
	-Also added comment not to write_milkyway if creating DC ILM
	-Can be done also in previous releases


dc_scripts/dc_top.tcl unique changes:
-------------------------------------

* Added section to prevent upwards boundary optimization from physical blocks
	-Requirement for hierarchical Formality verification flow
	-Recommended also for previous releases

* Added specification of DFT MAX integration strategy
	-Recommended also for previous releases

* Removed dft_drc from DFT output section for ADAPTIVE SCAN
	-Not supported (post-insertion) for ADAPTIVE SCAN at the top-level
	-Recommended also for previous releases

* Added missing report_congestion to reporting section
	-Recommended also for previous releases


dc_scripts/dc_MV.tcl unique changes:
------------------------------------

* enable_ao_synthesis variable setting removed
	-Now enabled by default
	-Fully supported by the MV flow (no reason to disable)

* Enhanced MV reporting section
	-Added the following reports: report_power_switch,
         report_level_shifter, report_isolation_cell, report_retention_cell
	-Now redirecting MV reports to report directory


dc_scripts/fm.tcl changes:
--------------------------

* Added note:  Due to MW schema changes in DC/ICC 2008.09, Formality won't support
  2008.09 DC/ICC MW design reading until 2008.12
	-Not recommended to use MW design input until 2008.12
	-Note: MW design input not supported for UPF flow (fm_MV.tcl)

* Removed case conversion for MW design name
	-Issue fixed in 2008.09


=============================================================================================

2007.12-SP2
===========

* Reference Methodology MV/MS reference script has been migrated to a UPF flow:
	-dc_scripts/dc_MV.tcl (top-down Multi-Voltage synthesis script)
	-dc_scripts/dc_MV.upf (example UPF file)

Note: MV hierarchical flow is not yet available.
      dc_scripts/dc_MV.tcl is for top-down use only.

common_setup.tcl changes:
-------------------------

* Added DESIGN_REF_DATA_PATH to be used as a prefix for absolute paths in the
  common_setup.tcl file variable settings.
	-Absolute paths are required for hierarchical RM flow

* Added additional power domain definition example
	-Note: Actual number of power domains is design specific.


dc_setup.tcl changes: None
---------------------

dc_scripts/dc(_MV)(_top).tcl common changes:
--------------------------------------------

* Added section to apply top-level operating conditions (required for MV flow)

* Added -congestion as optional new compile_ultra option

* hookup_testports output is now redirected to a separate log file

* Optional congestion reporting added to output section

* saif_map -stop is removed from the scripts
	-Syntax was incorrect
	-The saif_map database must be kept on
         for read_saif (before report_power) to work


dc_scripts/dc_top.tcl unique changes:
-------------------------------------

* Changes made to avoid design renaming/linking conflicts for hierarchical blocks
	-RTL versions of the hierarchical designs are now removed prior to saving elaborated design
	-link removed after reading elaborated design to avoid Presto rebuilding the RTL version
	-list_designs -show_file added to verify that the correct design versions have been linked

* Design data output section reorganized for consistency


dc_scripts/dc_MV.tcl unique changes:
------------------------------------

* Note that the new dc_MV.tcl script must be run with DC in UPF mode (-upf_mode
  option to dc_shell).

* Script checks and exits if not in UPF mode

* enable_ao_synthesis is now enabled by default in the script

* {DESIGN_NAME}.upf UPF file used for design MV setup
	-Design specific sections have been removed from the main script
	-Script will exit if necessary UPF loading is not successful
	-Final UPF is saved as a part of the design data output

* ${DESIGN_NAME}.set_voltage.tcl file read for design-specific set_voltage commands
	-set_voltage is not covered by UPF or SDC
	-Use this setup file also in ICC

* Added info about MV-specific set_scan_configuration options

* New MV script has single MV violation check after synthesis is completed
	-Intermediate MV operations not used in the UPF flow

* New MV Reports added to the output section


=============================================================================================


2007.12-SP1
===========

* Reference Methodology now includes scripts for a hierarchical flow:
	-dc_scripts/dc.tcl     (Existing top-down script can be used as a block-level script)
	-dc_scripts/dc_top.tcl (New top-level integration script)

Note: MV hierarchical flow is not yet available.
      dc_scripts/dc_MV.tcl is for top-down use only.

common_setup.tcl changes: None
-------------------------

dc_setup.tcl changes:
---------------------

* Added hierarhical flow designs variables:
	-DDC_HIER_DESIGNS:     List of DC hierarchical design names
	-DC_ILM_HIER_DESIGNS:  List of DC-ILM hierarchical design names
	-ICC_ILM_HIER_DESIGNS: List of ICC-ILM hierarchical design names

* Added Milkyway check_library command to verify Milkyway library setup

* Added section to include ICC-ILMs in link library
	-Using ICC-ILMs requires Milkyway library setup


dc_scripts/dc(_MV).tcl common changes:
--------------------------------------

* Clock-gating logic is now inserted using compile_ultra -gate_clock
	-Removed insert_clock_gating
	-Removed propagate_constraints -gate_clock
	-Added -gate_clock to default compile_ultra options
	-report_clock_gating moved to final reports section

* Power prediction is now commented out by default
        -Power prediction in topographical mode is enabled automatically when using power constraints
        -User can explicitly "set_power_prediction true" otherwise
        -Power prediction can not be enabled when using ICC-ILMs

* DFT output section has been reorganized
	-write_scan_def must be run BEFORE writing binary design files
	-Binary SCANDEF is now stored in DDC file
	-check_scan_def added to verify SCANDEF integrity

dc_scripts/dc.tcl unique changes:
---------------------------------

* Added read_sdc to read budgeted constraints for hierarhical flow (commented out)

* Added forced design uniquification with design name prefix for hierarchical flow
	-Prevents possible name collisions when integrating hierarchical designs at the top-level

* Added optional ILM creation step at the end for a hierarchical flow

Note: These new sections are specific for the hierarhical flow and are commented out by default.
      Uncomment if using this as a block-level script in a hierarchical flow.


=============================================================================================

2007.12
=======

* Reference Methodology now includes a Formality reference script: dc_scripts/fm.tcl

common_setup.tcl changes:
-------------------------

* Added MIN_ROUTING_LAYER and MAX_ROUTING_LAYER variables for set_ignored_layers in DC and ICC
	-DC now supports the same syntax as ICC for set_ignored_layers

* Removed VA? and VA?_CELLS variables from Multi-Voltage Common Variables section
	-VA name and VA cells are now derived from PD definitions and must match


dc_setup.tcl changes:
---------------------

* Script has been reorganized to allow shared setup by DC and Formality
	-Automatic conditional checks for dc_shell added
	-Milkyway setup variables moved up to common section for all tools

* DCT_IGNORED_ROUTING_LAYERS variable removed
	-Syntax of set_ignored_layers has changed to match ICC in 2007.12
	-Replaced by MIN_ROUTING_LAYER and MAX_ROUTING_LAYER in common_setup.tcl file

dc_scripts/dc(_MV).tcl common changes:
-------------------------------------

* Design Read
	-Save elaborated design after read for use in same release (could also be done in previous releases)

* Design Constraints
	-Added option to enable multiple clocks per register (MCPR) consideration in optimization and timing analysis
		-This can also be used in previous releases as needed
		-Requires that all clock domain exceptions be specified to avoid unnecessary runtime

* Physical Constraints
	-set_ignored_layers now uses -min_routing_layer & -max_routing_layer options like ICC

* Compile
	-Now have a compile_ultra -check_only option to verify library and design setup prior to
         running topographical mode synthesis

* Output Files
	-Added write_parasitics for topographical mode synthesis (could also be used in previous releases)

dc_scripts/dc_MV.tcl only changes:
---------------------------------

* create_voltage_area now uses -power_domain option to link VA to PD definition
	-name option and cell_list should no longer be used in 2007.12 (otherwise possible definition conflict)

* Additional level_shifter check and optional insertion added after insert_dft (needed for some libraries)

=============================================================================================

2007.03-SP1
===========

* Reference Methodology now includes a MV/MS reference script: dc_scripts/dc_MV.tcl

common_setup.tcl changes:
------------------------

* Added new section to define common multivoltage variables used by both DC and ICC

dc_setup.tcl changes:
---------------------

* Added conditional check for pre-existence of $mw_design_library before executing create_mw_lib


=============================================================================================

2007.03
=======

* First new version of DC-RM for 2007.03 release

dc_setup.tcl changes:
--------------------
* Added DCT_IGNORED_ROUTING_LAYERS
	-Using the same ignored layers as in P&R will improve correlation

* Changed MW library setup to use create_mw_lib and open_mw_lib instead of create_mw_design
	-New Milkyway UI is now consistent with ICC

* Added check_tlu_plus_files
	-Now supported in DC 2007.03 for TLU+ consistency check

dc_scripts/dc.tcl changes:
--------------------------
* Changes for new SAIF name mapping flow (Change your SAIF flow for 2007.03)
	-Removed power_preserve_rtl_hier_names, replaced by new flow
	-Added saif_map -start, read_saif -auto_map_names, saif_map -stop, saif_map -write_map for PTPX

* Default clock gating style is now recommended for most cases
	-set_clock_gating_style is now commented out

* Added set_ignored_layers that will use DCT_IGNORED_ROUTING_LAYERS defined in dc_setup.tcl
	-Using the same ignored layers as in P&R will improve correlation

* Physical constraints
	-extract_physical_constraints no longer needs scripted name translation in 2007.03
	-set_fuzzy_query_options added for extract_physical_constraints automatic name matching

* Compile
	-New -retime option for adaptive retiming added to list of recommended compile_ultra options

* DFT Setup
	-Added section explaining how to handle new test ports created in DC session
	-DFT setup for clock gating is changed in 2007.03
		-Removed: test_dft_drc_ungate_clocks true, test_dft_drc_ungate_internal_clocks, test_setup_additional_clock_pulse
		-Added: set_dft_drc_configuration -clock_gating_init_cycles 1
	-The following is no longer conditional. It is recommended to always use this setting to be consistent in all DC modes.
		set_dft_insertion_configuration -synthesis_optimization none

* DFT Incremental Compile will now always run compile_ultra -incremental -scan
	-DC now supports compile_ultra -incr in 2007.03

* SDC output cleanup to avoid writing RC info by setting the following variables (recommended also for 2006.06)
	set write_sdc_output_lumped_net_capacitance false
	set write_sdc_output_net_resistance false


=============================================================================================

2006.06-A
=========

*  Initial release of the DC-RM and only version for 2006.06