📄 12864a.lss.svn-base
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void write_lcd_data(unsigned char data)
{
582: 47 98 cbi 0x08, 7 ; 8
//We need to wait until both controller's busy bits are clear.
//Talk to the status (instruction) register.
CLR_RS;
//Tell the LCD we are going to be reading it
SET_RW;
584: 46 9a sbi 0x08, 6 ; 8
//Make port A high-impedance
LCD_DATA_DDR = LCD_DATA_ALL_INPUTS;
586: 11 b8 out 0x01, r1 ; 1
//Enable the selected controller's read data onto the port
SET_E;
588: 45 9a sbi 0x08, 5 ; 8
58a: 92 e2 ldi r25, 0x22 ; 34
58c: 9a 95 dec r25
58e: f1 f7 brne .-4 ; 0x58c <write_lcd_data+0xa>
_delay_us(6500);
//Wait for the busy bit to drop
while(PINA&0x80);
590: 07 99 sbic 0x00, 7 ; 0
592: fe cf rjmp .-4 ; 0x590 <write_lcd_data+0xe>
//Terminate the read
CLR_E;
594: 45 98 cbi 0x08, 5 ; 8
596: 92 e2 ldi r25, 0x22 ; 34
598: 29 2f mov r18, r25
59a: 2a 95 dec r18
59c: f1 f7 brne .-4 ; 0x59a <write_lcd_data+0x18>
_delay_us(6500); //stretch LOW E pulse width
//Write the data to the output latches of port A
LCD_DATA_PORT = data;
59e: 82 b9 out 0x02, r24 ; 2
//Tell the LCD that we are writing to it.
CLR_RW;
5a0: 46 98 cbi 0x08, 6 ; 8
//Aim at the data register.
SET_RS;
5a2: 47 9a sbi 0x08, 7 ; 8
//Strobe the E pin.
SET_E;
5a4: 45 9a sbi 0x08, 5 ; 8
//Go back to port A as an output
LCD_DATA_DDR = LCD_DATA_ALL_OUTPUTS; //125nS
5a6: 8f ef ldi r24, 0xFF ; 255
5a8: 81 b9 out 0x01, r24 ; 1
5aa: 89 2f mov r24, r25
5ac: 8a 95 dec r24
5ae: f1 f7 brne .-4 ; 0x5ac <write_lcd_data+0x2a>
_delay_us(6500); //stretch LOW E pulse width
//Terminate the write
CLR_E;
5b0: 45 98 cbi 0x08, 5 ; 8
5b2: 9a 95 dec r25
5b4: f1 f7 brne .-4 ; 0x5b2 <write_lcd_data+0x30>
_delay_us(6500); //stretch LOW E pulse width
}
5b6: 08 95 ret
000005b8 <UpdateLCD>:
//============================================================================
// Takes about 5.08ms (201.7KB/S) reading busy flag
void UpdateLCD(void)
{
5b8: 8f 92 push r8
5ba: 9f 92 push r9
5bc: af 92 push r10
5be: bf 92 push r11
5c0: cf 92 push r12
5c2: df 92 push r13
5c4: ef 92 push r14
5c6: ff 92 push r15
5c8: 0f 93 push r16
5ca: df 93 push r29
5cc: cf 93 push r28
5ce: 0f 92 push r0
5d0: 0f 92 push r0
5d2: cd b7 in r28, 0x3d ; 61
5d4: de b7 in r29, 0x3e ; 62
5d6: 00 e0 ldi r16, 0x00 ; 0
5d8: ee 24 eor r14, r14
5da: ff 24 eor r15, r15
5dc: 91 e0 ldi r25, 0x01 ; 1
5de: a9 2e mov r10, r25
5e0: 92 e0 ldi r25, 0x02 ; 2
5e2: b9 2e mov r11, r25
5e4: ae 0c add r10, r14
5e6: bf 1c adc r11, r15
5e8: 81 e4 ldi r24, 0x41 ; 65
5ea: c8 2e mov r12, r24
5ec: 82 e0 ldi r24, 0x02 ; 2
5ee: d8 2e mov r13, r24
5f0: ce 0c add r12, r14
5f2: df 1c adc r13, r15
right_data =& display[0][64];
for (page_address = 0; page_address <= 7; page_address++)
{
//Set Y address (page, or horizontal stripe of 8 pixels) (controller docs call this "X")
write_both_lcd_control_registers(0xB8 | page_address);
5f4: 80 2f mov r24, r16
5f6: 88 6b ori r24, 0xB8 ; 184
5f8: 0e 94 94 02 call 0x528 ; 0x528 <write_both_lcd_control_registers>
//Set X address 0 (right to left) (controller docs call this "Y")
write_both_lcd_control_registers(0x40);
5fc: 80 e4 ldi r24, 0x40 ; 64
5fe: 0e 94 94 02 call 0x528 ; 0x528 <write_both_lcd_control_registers>
602: 88 24 eor r8, r8
604: 99 24 eor r9, r9
606: c6 01 movw r24, r12
608: 88 0d add r24, r8
60a: 99 1d adc r25, r9
60c: 9a 83 std Y+2, r25 ; 0x02
60e: 89 83 std Y+1, r24 ; 0x01
610: f5 01 movw r30, r10
612: e8 0d add r30, r8
614: f9 1d adc r31, r9
for (column_address = 0; column_address <= 63; column_address++)
{
//Talk to the left controller only
SET_CS1;
616: 44 9a sbi 0x08, 4 ; 8
CLR_CS2;
618: 43 98 cbi 0x08, 3 ; 8
write_lcd_data(*left_data++);
61a: 80 81 ld r24, Z
61c: 0e 94 c1 02 call 0x582 ; 0x582 <write_lcd_data>
//Talk to the right controller only
CLR_CS1;
620: 44 98 cbi 0x08, 4 ; 8
SET_CS2;
622: 43 9a sbi 0x08, 3 ; 8
write_lcd_data(*right_data++);
624: e9 81 ldd r30, Y+1 ; 0x01
626: fa 81 ldd r31, Y+2 ; 0x02
628: 80 81 ld r24, Z
62a: 0e 94 c1 02 call 0x582 ; 0x582 <write_lcd_data>
62e: 08 94 sec
630: 81 1c adc r8, r1
632: 91 1c adc r9, r1
//Set X address 0 (right to left) (controller docs call this "Y")
write_both_lcd_control_registers(0x40);
for (column_address = 0; column_address <= 63; column_address++)
634: f0 e4 ldi r31, 0x40 ; 64
636: 8f 16 cp r8, r31
638: 91 04 cpc r9, r1
63a: 29 f7 brne .-54 ; 0x606 <UpdateLCD+0x4e>
//Initialize our source data pointers.
left_data =& display[0][0];
right_data =& display[0][64];
for (page_address = 0; page_address <= 7; page_address++)
63c: 0f 5f subi r16, 0xFF ; 255
63e: 80 e8 ldi r24, 0x80 ; 128
640: 90 e0 ldi r25, 0x00 ; 0
642: e8 0e add r14, r24
644: f9 1e adc r15, r25
646: 08 30 cpi r16, 0x08 ; 8
648: 49 f6 brne .-110 ; 0x5dc <UpdateLCD+0x24>
left_data += 64;
right_data += 64;
}
// Clear both chip selects
CLR_CS1;
64a: 44 98 cbi 0x08, 4 ; 8
CLR_CS2;
64c: 43 98 cbi 0x08, 3 ; 8
}
64e: 0f 90 pop r0
650: 0f 90 pop r0
652: cf 91 pop r28
654: df 91 pop r29
656: 0f 91 pop r16
658: ff 90 pop r15
65a: ef 90 pop r14
65c: df 90 pop r13
65e: cf 90 pop r12
660: bf 90 pop r11
662: af 90 pop r10
664: 9f 90 pop r9
666: 8f 90 pop r8
668: 08 95 ret
0000066a <ResetLCD>:
void ResetLCD(void)
{
66a: 42 98 cbi 0x08, 2 ; 8
66c: 82 e2 ldi r24, 0x22 ; 34
66e: 8a 95 dec r24
670: f1 f7 brne .-4 ; 0x66e <ResetLCD+0x4>
CLR_RESET;
_delay_us(6500);
SET_RESET;
672: 42 9a sbi 0x08, 2 ; 8
}
674: 08 95 ret
00000676 <InitializeLCD>:
//============================================================================
void InitializeLCD(void)
{
676: 42 9a sbi 0x08, 2 ; 8
LCD_CTRL_PORT |= (1 << LCD_RST);
/* Never reading status, clear LCD_RW low for writes only
* Clear LCD_E to low
*/
CLR_RW;
678: 46 98 cbi 0x08, 6 ; 8
67a: 82 e2 ldi r24, 0x22 ; 34
67c: 8a 95 dec r24
67e: f1 f7 brne .-4 ; 0x67c <InitializeLCD+0x6>
_delay_us(6500);
LCD_CTRL_PORT &= ~(1 << LCD_E);
680: 45 98 cbi 0x08, 5 ; 8
//Display on
write_both_lcd_control_registers(0x3F);
682: 8f e3 ldi r24, 0x3F ; 63
684: 0e 94 94 02 call 0x528 ; 0x528 <write_both_lcd_control_registers>
//Set Start Line 0
write_both_lcd_control_registers(0xC0);
688: 80 ec ldi r24, 0xC0 ; 192
68a: 0e 94 94 02 call 0x528 ; 0x528 <write_both_lcd_control_registers>
//Clear the display memeory
memset(display, 0x00, sizeof(display));
68e: 21 e0 ldi r18, 0x01 ; 1
690: 32 e0 ldi r19, 0x02 ; 2
692: 40 e0 ldi r20, 0x00 ; 0
694: 54 e0 ldi r21, 0x04 ; 4
696: 60 e0 ldi r22, 0x00 ; 0
698: 70 e0 ldi r23, 0x00 ; 0
69a: c9 01 movw r24, r18
69c: 0e 94 f7 03 call 0x7ee ; 0x7ee <memset>
}
6a0: 08 95 ret
000006a2 <Initialize_And_Start_Timer_0_LCD_Contrast_PWM>:
#include "timer.h"
void Initialize_And_Start_Timer_0_LCD_Contrast_PWM(void)
{
6a2: 14 bc out 0x24, r1 ; 36
//Stop the timer for now.
TCCR0A=0x00;
//Make sure the interrupt is disabled.
TIMSK0=0;
6a4: 10 92 6e 00 sts 0x006E, r1
//Reset the hardware timer count. The timer is stopped.
TCNT0=0;
6a8: 16 bc out 0x26, r1 ; 38
//Set the compare to 112.
OCR0A=112;
6aa: 80 e7 ldi r24, 0x70 ; 112
6ac: 87 bd out 0x27, r24 ; 39
//Enable the counter.
// 16MHz/1 = 16,000,000Hz
// 16,000,000/64 = 250,000Hz
TCCR0A = (1 << WGM00) | (1 << COM0A1);
6ae: 81 e8 ldi r24, 0x81 ; 129
6b0: 84 bd out 0x24, r24 ; 36
// TCCR0B = (1 << CS00) | (1 << CS01);
TCCR0B = (1 << CS01);
6b2: 82 e0 ldi r24, 0x02 ; 2
6b4: 85 bd out 0x25, r24 ; 37
}
6b6: 08 95 ret
000006b8 <Initialize_And_Start_Timer_1_32_Hz_and_Backlight>:
//============================================================================
void Initialize_And_Start_Timer_1_32_Hz_and_Backlight(void)
{
6b8: e0 e8 ldi r30, 0x80 ; 128
6ba: f0 e0 ldi r31, 0x00 ; 0
6bc: 10 82 st Z, r1
//Stop the timer for now.
TCCR1A=0x00;
TCCR1B=0x00;
6be: a1 e8 ldi r26, 0x81 ; 129
6c0: b0 e0 ldi r27, 0x00 ; 0
6c2: 1c 92 st X, r1
//Make sure the interrupt is disabled
TIMSK1=0;
6c4: 10 92 6f 00 sts 0x006F, r1
//Reset the hardware timer count. The timer is stopped.
TCNT1=0;
6c8: 10 92 85 00 sts 0x0085, r1
6cc: 10 92 84 00 sts 0x0084, r1
//Set the compare to 255 = 100%, LCD backlight is on.
OCR1A=255;
6d0: 8f ef ldi r24, 0xFF ; 255
6d2: 90 e0 ldi r25, 0x00 ; 0
6d4: 90 93 89 00 sts 0x0089, r25
6d8: 80 93 88 00 sts 0x0088, r24
// TCCR1A:
// COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10
// 0 1 0 0 0 0 0 1
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