📄 12864a.lss.svn-base
字号:
12864A.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000828 00000000 00000000 00000074 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .bss 00000401 00800200 00000828 0000089c 2**0
ALLOC
2 .debug_aranges 00000080 00000000 00000000 0000089c 2**0
CONTENTS, READONLY, DEBUGGING
3 .debug_pubnames 0000022d 00000000 00000000 0000091c 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_info 00000942 00000000 00000000 00000b49 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_abbrev 000003b4 00000000 00000000 0000148b 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_line 000007ec 00000000 00000000 0000183f 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_frame 00000120 00000000 00000000 0000202c 2**2
CONTENTS, READONLY, DEBUGGING
8 .debug_str 000002f1 00000000 00000000 0000214c 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_loc 00000147 00000000 00000000 0000243d 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <__vectors>:
0: 0c 94 66 02 jmp 0x4cc ; 0x4cc <__ctors_end>
4: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
8: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
10: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
14: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
18: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
1c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
20: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
24: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
28: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
2c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
30: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
34: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
38: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
3c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
40: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
44: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
48: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
4c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
50: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
54: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
58: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
5c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
60: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
64: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
68: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
6c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
70: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
74: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
78: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
7c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
80: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
84: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
88: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
8c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
90: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
94: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
98: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
9c: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
a0: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
a4: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
a8: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
ac: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
b0: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
b4: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
b8: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
bc: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
c0: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
c4: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
c8: 0c 94 87 02 jmp 0x50e ; 0x50e <__bad_interrupt>
000000cc <boot_logo>:
cc: f0 fc 0e 07 03 03 03 07 0e 0c 00 ff ff 83 83 83 ................
dc: 83 83 c7 fe 7c 00 03 0f 3c f0 c0 c0 f0 3c 0f 03 ....|...<....<..
ec: 00 3c 7e e7 c3 c3 c3 c3 c7 8e 0c 00 03 03 03 ff .<~.............
fc: ff 03 03 03 00 00 e0 fc 1f 1f fc e0 00 00 00 00 ................
10c: ff ff 00 00 00 00 00 00 00 00 00 00 ff ff c3 c3 ................
11c: c3 c3 c3 c3 03 03 f0 fc 0e 07 03 03 07 0e fc f0 ................
12c: 00 00 ff ff 0e 38 f0 c0 00 00 ff ff 00 03 03 03 .....8..........
13c: ff ff 03 03 03 00 03 03 03 03 c3 e3 33 1f 0f 03 ............3...
14c: 03 0f 1c 38 30 30 30 38 1c 0c 00 3f 3f 01 01 03 ...80008...??...
15c: 07 0f 1d 38 30 00 00 00 00 00 3f 3f 00 00 00 00 ...80.....??....
16c: 00 0c 1c 38 30 30 30 30 39 1f 0f 00 00 00 00 3f ...800009......?
17c: 3f 00 00 00 38 bf 87 86 86 06 06 07 bf b8 80 80 ?...8...........
18c: bf bf 30 30 30 b0 b0 b0 30 30 00 00 3f 3f 80 80 ..000...00..??..
19c: 80 80 00 00 00 00 03 0f 9c b8 30 30 38 9c 8f 83 ..........008...
1ac: 00 00 3f 3f 80 80 80 03 07 1c 3f bf 80 80 00 00 ..??......?.....
1bc: 3f 3f 00 00 80 80 30 3c 3e 33 b1 b0 b0 30 30 30 ??....0<>3...000
...
1d4: 00 00 80 c0 e0 70 38 1c 0c 0c 1c 38 70 20 00 00 .....p8....8p ..
1e4: 80 c0 e0 70 38 1c 0c 0c 1c 38 70 e0 c0 80 00 00 ...p8....8p.....
...
1fc: 00 00 3c 7f c3 80 80 c0 61 21 c0 fe 3f 09 08 08 ..<.....a!..?...
20c: 08 80 e0 78 3e 27 21 3f fe c0 00 3c 7f 83 80 88 ...x>'!?...<....
21c: c8 79 39 00 00 06 e3 ff 1f 01 00 c0 e1 b1 98 8f .y9.............
22c: 07 00 76 ff 88 88 7f 37 00 7c ff 8b c4 7d 39 30 ..v....7.|...}90
23c: 38 2c e6 ff 3f 21 80 e0 78 3e 27 21 3f fe c0 00 8,..?!..x>'!?...
24c: 80 80 80 80 80 80 98 9c 9e 9f 9f 9f 9f 80 80 80 ................
25c: 80 00 00 00 f8 fc fe ff ff ff ff 00 00 80 80 80 ................
26c: 80 80 80 9f 9f 9f 9f 9e 9c 98 80 80 80 80 80 80 ................
27c: 00 80 00 00 80 00 00 80 00 00 80 80 80 80 00 00 ................
28c: 80 00 00 80 00 00 80 00 00 80 00 00 80 00 00 80 ................
29c: 00 00 80 00 00 80 00 00 80 00 00 80 c0 e0 f0 38 ...............8
2ac: 1c 8e 06 06 8e 1c 38 f0 e0 80 80 00 00 80 00 00 ......8.........
2bc: 80 00 00 80 00 00 80 00 00 80 00 00 80 00 00 80 ................
2cc: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
2dc: ff 00 00 00 ff ff ff ff ff ff ff 00 00 99 99 99 ................
2ec: 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 ................
2fc: 00 c0 e0 b0 b8 9c 8e 86 83 83 81 81 81 83 83 87 ................
30c: 8e 9c b8 f0 e0 80 80 80 80 80 80 80 80 80 80 80 ................
31c: 80 80 80 80 80 80 80 80 c0 f0 bc 9f 87 81 80 80 ................
32c: 80 80 80 80 80 80 80 80 83 8f be f8 e0 80 80 80 ................
33c: 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 ................
34c: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
35c: ff 00 00 00 ff ff ff ff ff ff ff 00 00 99 99 99 ................
36c: 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 ................
37c: 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 ................
38c: 01 01 01 01 01 03 0f 1d 79 f1 c1 81 01 01 01 01 ........y.......
39c: 01 01 81 c1 e1 79 1d 0f 03 01 01 01 01 01 01 01 .....y..........
3ac: 01 01 01 01 01 01 01 01 01 01 01 01 07 1f 7d f1 ..............}.
3bc: c1 01 01 01 01 01 01 01 01 01 01 01 c1 f1 7f 1f ................
3cc: 01 01 01 01 01 01 19 39 79 f9 f9 f9 f9 01 01 01 .......9y.......
3dc: 01 00 00 00 1f 3f 7f ff ff ff ff 00 00 01 01 01 .....?..........
3ec: 01 01 01 f9 f9 f9 f9 79 39 19 01 01 01 01 01 01 .......y9.......
3fc: 00 01 00 00 01 00 00 01 00 00 01 00 00 01 00 00 ................
40c: 01 00 00 01 00 00 01 00 00 01 01 01 03 07 06 07 ................
41c: 06 07 03 01 00 01 00 00 01 00 00 01 00 00 01 00 ................
42c: 00 01 00 00 01 00 00 01 00 00 01 00 00 01 00 03 ................
43c: 07 1e 38 f1 c0 80 81 80 c0 f1 78 1f 07 01 00 01 ..8.......x.....
...
454: 00 00 01 03 07 0e 1c 38 30 30 38 1c 0e 04 00 00 .......8008.....
464: 01 03 07 0e 1c 38 30 30 38 1c 0e 07 03 01 00 00 .....8008.......
...
47c: 00 4c 92 92 92 64 00 fe 04 08 04 fe 00 fc 22 22 .L...d........""
48c: 22 fc 00 fe 80 80 80 80 00 fe 80 80 80 80 00 00 "...............
49c: 00 00 00 78 94 92 92 60 00 d8 20 20 d8 00 00 6c ...x...`.. ...l
4ac: 92 92 92 6c 00 00 00 00 00 02 02 fe 02 02 00 fe ...l............
4bc: 92 92 92 82 01 c7 29 11 29 c6 00 02 02 fe 02 02 ......).).......
000004cc <__ctors_end>:
4cc: 11 24 eor r1, r1
4ce: 1f be out 0x3f, r1 ; 63
4d0: cf ef ldi r28, 0xFF ; 255
4d2: d1 e2 ldi r29, 0x21 ; 33
4d4: de bf out 0x3e, r29 ; 62
4d6: cd bf out 0x3d, r28 ; 61
4d8: 00 e0 ldi r16, 0x00 ; 0
4da: 0c bf out 0x3c, r16 ; 60
000004dc <__do_copy_data>:
4dc: 12 e0 ldi r17, 0x02 ; 2
4de: a0 e0 ldi r26, 0x00 ; 0
4e0: b2 e0 ldi r27, 0x02 ; 2
4e2: e8 e2 ldi r30, 0x28 ; 40
4e4: f8 e0 ldi r31, 0x08 ; 8
4e6: 00 e0 ldi r16, 0x00 ; 0
4e8: 0b bf out 0x3b, r16 ; 59
4ea: 02 c0 rjmp .+4 ; 0x4f0 <__do_copy_data+0x14>
4ec: 07 90 elpm r0, Z+
4ee: 0d 92 st X+, r0
4f0: a0 30 cpi r26, 0x00 ; 0
4f2: b1 07 cpc r27, r17
4f4: d9 f7 brne .-10 ; 0x4ec <__do_copy_data+0x10>
000004f6 <__do_clear_bss>:
4f6: 16 e0 ldi r17, 0x06 ; 6
4f8: a0 e0 ldi r26, 0x00 ; 0
4fa: b2 e0 ldi r27, 0x02 ; 2
4fc: 01 c0 rjmp .+2 ; 0x500 <.do_clear_bss_start>
000004fe <.do_clear_bss_loop>:
4fe: 1d 92 st X+, r1
00000500 <.do_clear_bss_start>:
500: a1 30 cpi r26, 0x01 ; 1
502: b1 07 cpc r27, r17
504: e1 f7 brne .-8 ; 0x4fe <.do_clear_bss_loop>
506: 0e 94 89 02 call 0x512 ; 0x512 <main>
50a: 0c 94 12 04 jmp 0x824 ; 0x824 <_exit>
0000050e <__bad_interrupt>:
50e: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>
00000512 <main>:
#include "low_lcd.h"
#include "timer.h"
#include "logo_screen.h"
int main(void)
{
512: 0e 94 9c 03 call 0x738 ; 0x738 <Initialize_GPIO>
// Initialize the ports
Initialize_GPIO();
// Initialize timers, PWMs, and LCD
Initialize_contrast_backlight_and_LCD();
516: 0e 94 c9 03 call 0x792 ; 0x792 <Initialize_contrast_backlight_and_LCD>
UpdateLCD();
51a: 0e 94 dc 02 call 0x5b8 ; 0x5b8 <UpdateLCD>
can be achieved.
*/
void
_delay_loop_1(uint8_t __count)
{
__asm__ volatile (
51e: 91 e0 ldi r25, 0x01 ; 1
520: 89 2f mov r24, r25
522: 8a 95 dec r24
524: f1 f7 brne .-4 ; 0x522 <main+0x10>
526: fc cf rjmp .-8 ; 0x520 <main+0xe>
00000528 <write_both_lcd_control_registers>:
//============================================================================
volatile unsigned char display_status;
//============================================================================
void write_both_lcd_control_registers(unsigned char data)
{
528: 28 2f mov r18, r24
//We need to wait until both controller's busy bits are clear.
//Talk to the status (instruction) register.
CLR_RS;
52a: 47 98 cbi 0x08, 7 ; 8
//Tell the LCD we are going to be reading it
SET_RW;
52c: 46 9a sbi 0x08, 6 ; 8
//Talk to the left controller only
SET_CS1;
52e: 44 9a sbi 0x08, 4 ; 8
CLR_CS2;
530: 43 98 cbi 0x08, 3 ; 8
//Make port A high-impedance so we can read from the LCD
LCD_DATA_DDR = LCD_DATA_ALL_INPUTS;
532: 11 b8 out 0x01, r1 ; 1
//Enable the selected controller's read data onto the port
SET_E;
534: 45 9a sbi 0x08, 5 ; 8
536: 82 e2 ldi r24, 0x22 ; 34
538: 8a 95 dec r24
53a: f1 f7 brne .-4 ; 0x538 <write_both_lcd_control_registers+0x10>
_delay_us(6500);
//Wait for the busy bit to drop
while(PINA&0x80);
53c: 07 99 sbic 0x00, 7 ; 0
53e: fe cf rjmp .-4 ; 0x53c <write_both_lcd_control_registers+0x14>
//Terminate the read
CLR_E;
540: 45 98 cbi 0x08, 5 ; 8
542: 82 e2 ldi r24, 0x22 ; 34
544: 98 2f mov r25, r24
546: 9a 95 dec r25
548: f1 f7 brne .-4 ; 0x546 <write_both_lcd_control_registers+0x1e>
_delay_us(6500); //stretch LOW E pulse width
//Talk to the right controller only
CLR_CS1;
54a: 44 98 cbi 0x08, 4 ; 8
SET_CS2;
54c: 43 9a sbi 0x08, 3 ; 8
54e: 98 2f mov r25, r24
550: 9a 95 dec r25
552: f1 f7 brne .-4 ; 0x550 <write_both_lcd_control_registers+0x28>
_delay_us(6500);
//Enable the selected controller's read data onto the port
SET_E;
554: 45 9a sbi 0x08, 5 ; 8
556: 8a 95 dec r24
558: f1 f7 brne .-4 ; 0x556 <write_both_lcd_control_registers+0x2e>
_delay_us(6500);
//Wait for the busy bit to drop
while(PINA&0x80);
55a: 07 99 sbic 0x00, 7 ; 0
55c: fe cf rjmp .-4 ; 0x55a <write_both_lcd_control_registers+0x32>
//Terminate the read
CLR_E;
55e: 45 98 cbi 0x08, 5 ; 8
560: 92 e2 ldi r25, 0x22 ; 34
562: 89 2f mov r24, r25
564: 8a 95 dec r24
566: f1 f7 brne .-4 ; 0x564 <write_both_lcd_control_registers+0x3c>
_delay_us(6500); //stretch LOW E pulse width
//Write the data to the output latches of port A
LCD_DATA_PORT = data;
568: 22 b9 out 0x02, r18 ; 2
//Tell the LCD that we are writing to it.
CLR_RW;
56a: 46 98 cbi 0x08, 6 ; 8
//Talk to both controllers (right controller already active)
SET_CS1;
56c: 44 9a sbi 0x08, 4 ; 8
//Strobe the E pin. We are still aimed at the status/instruction register.
SET_E;
56e: 45 9a sbi 0x08, 5 ; 8
//Go back to port A as an output
LCD_DATA_DDR = LCD_DATA_ALL_OUTPUTS;
570: 8f ef ldi r24, 0xFF ; 255
572: 81 b9 out 0x01, r24 ; 1
574: 89 2f mov r24, r25
576: 8a 95 dec r24
578: f1 f7 brne .-4 ; 0x576 <write_both_lcd_control_registers+0x4e>
_delay_us(6500); //stretch LOW E pulse width
CLR_E;
57a: 45 98 cbi 0x08, 5 ; 8
57c: 9a 95 dec r25
57e: f1 f7 brne .-4 ; 0x57c <write_both_lcd_control_registers+0x54>
_delay_us(6500); //stretch LOW E pulse width
}
580: 08 95 ret
00000582 <write_lcd_data>:
//============================================================================
// PORTC0_LCD_CS1 and PORTD6_LCD_CS2 must be set to select the desired
// controller
//----------------------------------------------------------------------------
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