ax88796.h

一个AVR 上的UIP移植程序

/*! \file ax88796.h \brief ASIX 88796 L Ethernet Interface Driver. */
//*****************************************************************************
//
// File Name	: 'ax88796.h'
// Title		: ASIX 88796 L Ethernet Interface Driver
// Author		: Pascal Stang
// Created		: 10/22/2002
// Revised		: 10/26/2002
// Version		: 0.1
// Target MCU	: Atmel AVR series
// Editor Tabs	: 4
//
// Description	: This include file is designed to contain items useful to all
//					code files and projects.
//
// Based in part on code by Louis Beaudoin (www.embedded-creations.com)
//
// This code is distributed under the GNU Public License
//		which can be found at http://www.gnu.org/licenses/gpl.txt
//
//*****************************************************************************

#ifndef AX88796_H
#define AX88796_H

#include "global.h"
#include "delay.h"
#include "compiler.h"

/*****************************************************************************
*
*  AVR hardware setup
*
*    External SRAM Interface:
*      The five NIC address lines are taken from A8-A12 (uses the
*      non-multiplexed address port so no latch is required)
*
*    General I/O Interface:
*      Two full ports are required for the address and data buses.  Two pins
*        from another port are used to control the read and write lines
*
*    One output pin is required for hard resetting the NIC
*
*****************************************************************************/

// set to 1 to use the External SRAM Interface - 0 for General I/O
#define MEMORY_MAPPED_NIC 0

#if MEMORY_MAPPED_NIC /*** NIC Interface through External SRAM Interface ****/
	// NIC is mapped from address 0x8000 - 0x9F00
	#define MEMORY_MAPPED_AX88796_OFFSET 0x8000
#else /************ NIC Interface through General I/O *******************/
	// AX88796 address port
	#define AX88796_ADDRESS_PORT        PORTC
	#define AX88796_ADDRESS_DDR         DDRC
	#define AX88796_ADDRESS_MASK		0x1F

	// AX88796 data port
	#define AX88796_DATA_PORT           PORTA
	#define AX88796_DATA_DDR            DDRA
	#define AX88796_DATA_PIN            PINA

	// AX88796 control port
	#define AX88796_CONTROL_PORT        PORTC
	#define AX88796_CONTROL_DDR         DDRC
	#define AX88796_CONTROL_READPIN     PC5
	#define AX88796_CONTROL_WRITEPIN    PC6

#endif /** NIC Interface **/

// AX88796 RESET pin
#define AX88796_RESET_PORT 	PORTD
#define AX88796_RESET_DDR 	DDRD
#define AX88796_RESET_PIN 	PD2

/*****************************************************************************
*
* MAC address for this interface
*
*****************************************************************************/
#define MYMAC_0 '0'
#define MYMAC_1 'F'
#define MYMAC_2 'F'
#define MYMAC_3 'I'
#define MYMAC_4 'C'
#define MYMAC_5 'E'


/*****************************************************************************
*
*  Ethernet constants
*
*****************************************************************************/
#define ETHERNET_MIN_PACKET_LENGTH	0x3C
#define ETHERNET_HEADER_LENGTH		0x0E

//******************************************************************
//*	ASIX 88796 L CONTROL REGISTER OFFSETS
//******************************************************************
// Page 0
#define CR		 	0x00
#define PSTART		0x01
#define PSTOP		0x02
#define BNRY		0x03
#define TSR			0x04
#define TPSR		0x04
#define TBCR0		0x05
#define NCR			0x05
#define TBCR1		0x06
#define ISR			0x07
#define RSAR0		0x08
#define CRDA0		0x08
#define RSAR1		0x09
#define CRDAL		0x09
#define RBCR0		0x0A
#define RBCR1		0x0B
#define RSR			0x0C
#define RCR			0x0C
#define TCR			0x0D
#define CNTR0		0x0D
#define DCR			0x0E
#define CNTR1		0x0E
#define IMR			0x0F
#define CNTR2		0x0F
#define RDMAPORT  	0x10
#define MEMR		0x14
#define TR			0x15
#define GPOC		0x17
#define GPI			0x17
#define SPP_DPR    	0x18
#define SSP_SPR		0x19
#define SSP_CPR		0x1A
#define RSTPORT		0x1F
// Page 1
#define PAR0      	0x01	// Page 1
#define PAR1      	0x02	// Page 1
#define PAR2      	0x03	// Page 1
#define PAR3      	0x04	// Page 1
#define PAR4      	0x05	// Page 1
#define PAR5      	0x06	// Page 1
#define CURR		0x07	// Page 1
#define CPR			0x07	// Page 1

//******************************************************************
//*	ASIX 88796 L CR REGISTER BIT DEFINITIONS
//******************************************************************
#define  PS1		0x80 
#define  PS0		0x40 
#define  RD2		0x20 
#define  RD1		0x10 
#define  RD0		0x08 
#define  TXP		0x04 
#define  START		0x02 
#define  STOP		0x01 
//******************************************************************
//*	ASIX 88796 L RCR REGISTER BIT DEFINITIONS
//******************************************************************
#define  INTT		0x40 
#define  MON		0x20 
#define  PRO		0x10 
#define  AM			0x08 
#define  AB			0x04 
#define  AR			0x02 
#define  SEP		0x01 
//******************************************************************
//*	ASIX 88796 L ISR REGISTER BIT DEFINITIONS
//******************************************************************
#define  RST		0x80
#define  RDC		0x40
#define  OVW		0x10
#define  RXE		0x08
#define  TXE		0x04
#define  PTX		0x02
#define  PRX		0x01
//******************************************************************
//*	ASIX 88796 L TEST REGISTER DEFINITIONS
//******************************************************************
#define  AUTOD		0x01 
#define  RST_B		0x02
#define  RST_10B	0x04
#define  RST_TXB	0x08
//******************************************************************
//*	ASIX 88796 L GPOC BITS DEFINITIONS
//******************************************************************
#define  GPO0		0x01
#define	 MPSEL		0x10
#define  MPSET		0x20
#define  PPDSET		0x40
//******************************************************************
//*	ASIX 88796 L MEMR BITS DEFINITIONS
//******************************************************************
#define  MDC		0x01
#define  MDIR		0x02
#define  MDI		0x04
#define  MDO		0x08
#define  EECS		0x10
#define  EEI		0x20
#define  EEO		0x40
#define  EECLK		0x80
//******************************************************************
//*	ASIX 88796 L GPI BITS DEFINITIONS
//******************************************************************
#define  GPI2		0x40
#define  GPI1		0x20
#define  GPI0		0x10
#define  I_SPD		0x04
#define  I_DPX		0x02
#define  I_LINK		0x01
//******************************************************************
//*	ASIX 88796 L TCR BITS DEFINITIONS
//******************************************************************
#define  FDU		0x80	// full duplex
#define  PD			0x40	// pad disable
#define  RLO		0x20	// retry of late collisions
#define  LB1		0x04	// loopback 1
#define  LB0		0x02	// loopback 0