📄 m500auc.lst
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474 2 waitFor = 0x04;
475 2 break;
476 2 case PCD_TRANSMIT: // LoAlert and IdleIRq
477 2 irqEn = 0x05;
478 2 waitFor = 0x04;
479 2 break;
480 2 case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert
481 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
482 2 irqEn = 0x3D;
483 2 waitFor = 0x04;
484 2 break;
485 2 default:
486 2 status = MI_UNKNOWN_COMMAND;
487 2 }
488 1 if (status == MI_OK)
489 1 {
C51 COMPILER V6.12 M500AUC 08/25/2007 20:27:21 PAGE 9
490 2 // Initialize uC Timer for global Timeout management
491 2 irqEn |= 0x20; // always enable timout irq
492 2 waitFor |= 0x20; // always wait for timeout
493 2
494 2 start_timeout(4000); // initialise and start guard timer for reader
495 2 // 50us resolution, 200ms
496 2
497 2 WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled
498 2 WriteIO(RegCommand,cmd); //start command
499 2
500 2 // wait for commmand completion
501 2 // a command is completed, if the corresponding interrupt occurs
502 2 // or a timeout is signaled
503 2
504 2 while (!(MpIsrInfo->irqSource & waitFor
505 2 || T2IR)); // wait for cmd completion or timeout
506 2
507 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
508 2 WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
509 2 SetBitMask(RegControl,0x04); // stop timer now
510 2
511 2 stop_timeout(); // stop timeout for reader
512 2 WriteIO(RegCommand,PCD_IDLE); // reset command register
513 2
514 2
515 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
516 2 { // timer 2 expired
517 3 status = MI_ACCESSTIMEOUT;
518 3 }
519 2 else
520 2 status = MpIsrInfo->status; // set status
521 2
522 2 if (status == MI_OK) // no timeout error occured
523 2 {
524 3 if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
525 3 {
526 4 if (tmpStatus & 0x01) // collision detected
527 4 {
528 5 info->collPos = ReadIO(RegCollpos); // read collision position
529 5 status = MI_COLLERR;
530 5 }
531 4 else
532 4 {
533 5 info->collPos = 0;
534 5 if (tmpStatus & 0x02) // parity error
535 5 {
536 6 status = MI_PARITYERR;
537 6 }
538 5 }
539 4 if (tmpStatus & 0x04) // framing error
540 4 {
541 5 status = MI_FRAMINGERR;
542 5 }
543 4 if (tmpStatus & 0x10) // FIFO overflow
544 4 {
545 5 FlushFIFO();
546 5 status = MI_OVFLERR;
547 5 }
548 4 if (tmpStatus & 0x08) //CRC error
549 4 {
550 5 status = MI_CRCERR;
551 5 }
C51 COMPILER V6.12 M500AUC 08/25/2007 20:27:21 PAGE 10
552 4 if (status == MI_OK)
553 4 status = MI_NY_IMPLEMENTED;
554 4 // key error occures always, because of
555 4 // missing crypto 1 keys loaded
556 4 }
557 3 // if the last command was TRANSCEIVE, the number of
558 3 // received bits must be calculated - even if an error occured
559 3 if (cmd == PCD_TRANSCEIVE)
560 3 {
561 4 // number of bits in the last byte
562 4 lastBits = ReadIO(RegSecondaryStatus) & 0x07;
563 4 if (lastBits)
564 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
565 4 else
566 4 info->nBitsReceived += info->nBytesReceived * 8;
567 4 }
568 3 }
569 2 else
570 2 {
571 3 info->collPos = 0x00;
572 3 }
573 2 }
574 1 MpIsrInfo = 0; // reset interface variables for ISR
575 1 MpIsrOut = 0;
576 1 MpIsrIn = 0;
577 1 return status;
578 1 }
579
580 //////////////////////////////////////////////////////////////////////
581 // S E T A B I T M A S K
582 ///////////////////////////////////////////////////////////////////////
583 char SetBitMask(unsigned char reg,unsigned char mask) //
584 {
585 1 char idata tmp = 0x0;
586 1
587 1 tmp = ReadIO(reg);
588 1 WriteIO(reg,tmp | mask); // set bit mask
589 1 return 0x0;
590 1 }
591
592 //////////////////////////////////////////////////////////////////////
593 // C L E A R A B I T M A S K
594 ///////////////////////////////////////////////////////////////////////
595 char ClearBitMask(unsigned char reg,unsigned char mask) //
596 {
597 1 char idata tmp = 0x0;
598 1
599 1 tmp = ReadIO(reg);
600 1 WriteIO(reg,tmp & ~mask); // clear bit mask
601 1 return 0x0;
602 1 }
603
604 ///////////////////////////////////////////////////////////////////////
605 // F L U S H F I F O
606 ///////////////////////////////////////////////////////////////////////
607 void FlushFIFO(void)
608 {
609 1 SetBitMask(RegControl,0x01);
610 1 }
611
612 ///////////////////////////////////////////////////////////////////////
613 // M I F A R E M O D U L E R E S E T
C51 COMPILER V6.12 M500AUC 08/25/2007 20:27:21 PAGE 11
614 ///////////////////////////////////////////////////////////////////////
615 char M500PcdReset(void)
616 {
617 1 char idata status = MI_OK;
618 1
619 1 RC500RST = 0; // clear reset pin
620 1 delay_1ms(25); // wait for 25ms
621 1 RC500RST = 1; // reset RC500
622 1 delay_50us(50); // wait for 2.5ms
623 1 RC500RST = 0; // clear reset pin
624 1
625 1 start_timeout(42000); // count down with a period of 50 us
626 1 // 42000 * 50 us = 2.1 s
627 1
628 1 // wait until reset command recognized
629 1 while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);
630 1 // while reset sequence in progress
631 1 while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR);
632 1
633 1 stop_timeout(); // stop timeout counter
634 1
635 1 if (T2IR) // If reader timeout occurs
636 1 {
637 2 status = MI_RESETERR; // respose of reader IC is not correct
638 2 T2IR = 0;
639 2 }
640 1 else
641 1 {
642 2 WriteRawIO(RegPage,0x80); // Dummy access in order to determine the bus
643 2 // configuration
644 2 // necessary read access
645 2 // after first write access, the returned value
646 2 // should be zero ==> interface recognized
647 2 if (ReadRawIO(RegCommand) != 0x00)
648 2 {
649 3 status = MI_INTERFACEERR;
650 3 }
651 2 WriteRawIO(RegPage,0x00); // configure to linear address mode
652 2
653 2 }
654 1 return status;
655 1 }
656
657 ///////////////////////////////////////////////////////////////////////
658 // M I F A R E M O D U L E C O N F I G U R A T I O N
659 ///////////////////////////////////////////////////////////////////////
660 char M500PcdConfig(void)
661 {
662 1 char idata status;
663 1 char idata i;
664 1 char idata j;
665 1
666 1 if ((status = M500PcdReset()) == MI_OK)
667 1 {
668 2 // test clock Q calibration - value in the range of 0x46 expected
669 2 WriteIO(RegClockQControl,0x0);
670 2 WriteIO(RegClockQControl,0x40);
671 2 delay_50us(2); // wait approximately 100 us - calibration in progress
672 2 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
673 2 // further calibration
674 2
675 2 // The following values for RegBitPhase and
C51 COMPILER V6.12 M500AUC 08/25/2007 20:27:21 PAGE 12
676 2 // RegRxThreshold represents an optimal
677 2 // value for our demo package. For user
678 2 // implementation some changes could be
679 2 // necessary
680 2 // initialize bit phase
681 2 WriteIO(RegBitPhase,0xAD);
682 2
683 2 // initialize minlevel
684 2 WriteIO(RegRxThreshold,0xFF);
685 2
686 2 // disable auto power down
687 2 WriteIO(RegRxControl2,0x01);
688 2
689 2 // Depending on the processing speed of the
690 2 // operation environment, the waterlevel
691 2 // can be adapted. (not very critical for
692 2 // mifare applications)
693 2 // initialize waterlevel to value 4
694 2 WriteIO(RegFIFOLevel,0x04);
695 2
696 2 //Timer configuration
697 2 WriteIO(RegTimerControl,0x02); // TStopRxEnd=0,TStopRxBeg=0,
698 2 // TStartTxEnd=1,TStartTxBeg=0
699 2 // timer must be stopped manually
700 2 M500PcdSetTmo(1); // short timeout
701 2
702 2 WriteIO(RegIRqPinConfig,0x03); // interrupt active low enable
703 2
704 2 M500PcdRfReset(1); // Rf - reset and enable output driver
705 2
706 2 // initialize internal key memory
707 2 for (i = 0; i < 16; i++)
708 2 for (j = 0; j < 12; j++)
709 2 MKeys[i][j] = 0xff;
710 2 }
711 1 return status;
712 1 }
713
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