memsetup.s

学习嵌入式LINUX的好东西

/*
 * Intel PXA255 Processor Developers Manual January, 2004
 * 6.11Hardware, Watchdog, or Sleep Reset Operation
 * p 261 - 263
 */

#include <hardware.h>
#include <board.h>


.global setup_memory


#define SDRAM_BASE			0xA0000000

#define _CKEN				0x04
#define _OSCC				0x08

#define CLKCFG_FAST_BUS		0x08
#define CLKCFG_B			0x08
#define CLKCFG_HALF_TURBO	0x04
#define CLKCFG_HT			0x04
#define CLKCFG_FCS			0x02
#define CLKCFG_F			0x02
#define CLKCFG_TURBO		0x01

/***** Setup Static & Dynamic Memory *****/
@ r0, r1, r2 corrupted.
.func setup_memory
setup_memory :
	@ change cpu speed function
	ldr		r1, =CCCR
	ldr		r0, =_CCCR
	str		r0, [r1]					@ set CCCR
@	mov		r0, #(CLKCFG_TURBO | CLKCFG_FCS | CLKCFG_FAST_BUS)
@	mov		r0, #(CLKCFG_HT | CLKCFG_FCS)
@	mcr		p14, 0, r0, c6, c0, 0		@ enter the frequency change sequence

@ 1. After hardware reset, complete a power-on wait period of 200 s, which allows the internal
@    clocks that generate SDCLK to stabilize. Enable MDREFR:K0RUN and E0PIN for
@    Synchronous Static memory. When MDREFR is written, a refresh interval value
@    (MDREFR:DRI) must also be written. The following writes are allowed:
	@ delay 200 us
	ldr		r1, =OSCR
	ldr		r0, [r1]
	add		r2, r0, #0x300
 1:	ldr		r0, [r1]
	cmp		r0, r2
	blt		1b

	@ a. Write MSC0, MSC1, MSC2
	@ MSC0 : CS0, CS1
	ldr		r1, =MSC0
	ldr		r2, =_MSC0
	bic		r2, r2, #0x08				@ clear RBWx on _MSC0
	ldr		r0, [r1]					@ load at MSC0
	and		r0, r0, #0x08				@ Get bit width(RBWx) of cs0. Generated by ROM_SEL pin
	orr		r0, r0, r2					@ make value for MSC0
	str		r0, [r1]					@ store at MSC0
	@ MSC1 : CS2, CS3
	ldr		r1, =MSC1
	ldr		r0, =_MSC1
	str		r0, [r1]
	@ MSC2 : CS4, CS5
	ldr		r1, =MSC2
	ldr		r0, =_MSC2
	str		r0, [r1]


	@ b. Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1
	@ write MECR
	ldr		r1, =MECR
	ldr		r0, =_MECR
	str		r0, [r1]
	@ write MCMEM0
	ldr		r1, =MCMEM0
	ldr		r0, =_MCMEM0
	str		r0, [r1]
	@ write MEMEM1
	ldr		r1, =MCMEM1
	ldr		r0, =_MCMEM1
	str		r0, [r1]
	@ write MCATT0
	ldr		r1, =MCATT0
	ldr		r0, =_MCATT0
	str		r0, [r1]
	@ write MCATT1
	ldr		r1, =MCATT1
	ldr		r0, =_MCATT1
	str		r0, [r1]
	@ write MCIO0
	ldr		r1, =MCIO0
	ldr		r0, =_MCIO0
	str		r0, [r1]
	@ write MCIO1
	ldr		r1, =MCIO1
	ldr		r0, =_MCIO1
	str		r0, [r1]


@ c. Write MDREFR:K0RUN and MDREFR:E0PIN. Configure MDREFR:K0DB2. Retain
@    the current values of MDREFR:APD and MDREFR:SLFRSH. MDREFR:DRI must
@    contain a valid value. Deassert MDREFR:KxFREE.
	ldr		r1, =MDREFR

	ldr		r2, =_MDREFR_ED
	ldr		r3, [r1]

	mov		r2, r2, lsl #20		@ get only DRI from default config
	mov		r2, r2, lsr #20

	mov		r3, r3, lsr #12		@ get all without DRI from MDREFR register
	mov		r3, r3, lsl #12
	bic		r3, r3, #(MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE)

	orr		r0, r2, r3
	str		r0, [r1]


	// 2.
	// We don't have Synchronous Static Memory and don't want to
	// mess with SXCNFG or the like so we are leaving out this
	// step.

	// 3.
	// We don't bother to do this step as it does not seem to have
	// been done previously (actually maybe Self-Refresh Disable should
	// be here.)

	// 4.
	// Here we will setup the SDCLK's but WILL NOT enable them. We
	// need to reload MDREFR for this.
	ldr		r1, =MDREFR
	@ configure K1RUN, K1DB2, K2RUN, K2DB2
	ldr		r0, =_MDREFR_ED
	and		r0, r0, #(MDREFR_K1RUN | MDREFR_K1DB2 | MDREFR_K2RUN | MDREFR_K2DB2)
	ldr		r2, [r1]
	bic		r2, r2, #(MDREFR_K1RUN | MDREFR_K1DB2 | MDREFR_K2RUN | MDREFR_K2DB2)
	orr		r0, r0, r2
	str		r0, [r1]
	@ clear SLFRSH
	ldr		r0, [r1]
	bic		r0, r0, #MDREFR_SLFRSH
	str		r0, [r1]

	// 5.
	// Finally, we Enable the Various SDCLK's and let it run.
	// Also, enable the free-running clocks (not mentioned in the manual).
	ldr		r1, =MDREFR
	ldr		r2, =_MDREFR_ED
	ldr		r3, [r1]
	ldr		r0, =(MDREFR_E0PIN | MDREFR_E1PIN | MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE)
	and		r2, r2, r0
	bic		r3, r3, r0
	orr		r0, r2, r3
	str		r0, [r1]
	nop
	nop

	//Step 4 in Intel's code
@ disable all banks
@ clear DEx in MDCNFG
	ldr		r1, =MDCNFG
	ldr		r0, =_MDCNFG_ED
	bic		r0, r0, #(MDCNFG_DE0 | MDCNFG_DE1)		@ disable sdram bank 0, 1
	bic		r0, r0, #(MDCNFG_DE2 | MDCNFG_DE3)		@ disable sdram bank 0, 1
	str		r0, [r1]

	@ delay 200 us
	ldr		r1, =OSCR
	ldr		r0, [r1]
	add		r2, r0, #0x300
 1:	ldr		r0, [r1]
	cmp		r0, r2
	blt		1b



	// Step 6 in Intel's code
	// turn everything off
	mov		r0, #0x78
	mcr		p15, 0, r0, c1, c0, 0


	//Step 7 in Intel's code
	//Access memory that has not been enabled for CBR refresh cycles (8)

@ on a hardware reset in systems, trigger the specified number (typically eight) of
@ refresh cycles by attempting non-burst read or write accesses to any disabled SDRAM bank.
@ check hardware reset. if not, skip this.
	ldr		r1, =RCSR
	ldr		r0, [r1]
	tst		r0, #RCSR_HWR
	beq		2f				@ if not hardware reset, do nothing.

	ldr		r2, =_MDCNFG_ED
	ands	r0, r2, #MDCNFG_DE0		@ bank 0
	beq		1f
	ldr		r0, =0xA0000000
   .rept 8
	str		r0, [r0]
   .endr
 1:	ands	r0, r2, #MDCNFG_DE1		@ bank 1
	beq		1f
	ldr		r0, =0xA4000000
   .rept 8
	str		r0, [r0]
   .endr
 1:	ands	r0, r2, #MDCNFG_DE2		@ bank 2
	beq		1f
	ldr		r0, =0xA8000000
   .rept 8
	str		r0, [r0]
   .endr
 1:	ands	r0, r2, #MDCNFG_DE3		@ bank 3
	beq		2f
	ldr		r0, =0xAC000000
   .rept 8
	str		r0, [r0]
   .endr
 2:


	//Step 8 is blank in Intel's code, though they mention dcache should
	//be enabled here if it is desired (we don't care)

	//Step 9
	ldr		r1, =MDCNFG
	ldr		r0, =_MDCNFG_ED
	str		r0, [r1]


	//Step 10
	//write MDMRS again
	ldr		r1, =MDMRS
	ldr		r0, =_MDMRS
	str		r0, [r1]


	//Step 11
	//are we A1_Cotulla?
	ldr		r1, =MDREFR
	ldr		r0, =_MDREFR_ED
	ands	r0, r0, #MDREFR_APD
	beq		2f
	ldr		r0, [r1]
	orr		r0, r0, #MDREFR_APD
	str		r0, [r1]
 2:

	mov		pc, lr				@ return

.endfunc