📄 3xa_sensor.h
字号:
1033 {0x6f, 0x11},
1034 {0x70, 0x11},
1035 {0x71, 0x22},
1036 {0x72, 0x22},
1037 {0x73, 0x11},
1038 {0x74, 0x11},
1039 {0x75, 0x22},
1040 {0x76, 0x22},
1041 {0x77, 0x11},
1042 {0x78, 0x33},
1043 {0x79, 0x33},
1044 {0x7a, 0x33},
1045 {0x7b, 0x33},
1046 {0x7c, 0x33},
1047 {0x7d, 0x33},
1048 {0x7e, 0x33},
1049 {0x7f, 0x33},
1050 {0xfc, 0x01},
1051 {0x02, 0x02},
1052 {0xfc, 0x02},
1053 {0x30, 0x83},
1054 {0x44, 0x5b}, // clamp enable
1055 {0x55, 0x03},
1056 {0xfc, 0x00},
1057 {0x62, 0x02},
1058 {0xfc, 0x04},
1059 {0xee, 0x08},
1060 {0xfc, 0x03},
1061 {0x2e, 0x08},
1062 {0xfc, 0x02},
1063 {0x11, 0x11},
1064 {0xfc, 0x01},
1065 {0x4d, 0x08}, // RV con, Red pixel Ordering
1066 //{0x01, 0x00}, // PCLK
1067 {0x01, 0x01}, // Inversion PCLK
1068 {0xfc, 0x00},
1069 {0x02, 0x00}, // UXGA Size Out
1070
1071 // for 800x600(SVGA)
1072 // Page 0
1073 {0xfc, 0x00},
1074 {0x02, 0x09}, // 800*600 sub-sampling
1075 // Page 9
1076 {0xfc, 0x09}, // 800*600 shading delta value
1077 {0x1D, 0xFF},
1078 {0x1E, 0xFF},
1079 {0x1F, 0xFF},
1080 {0x20, 0xFF},
1081 {0x21, 0xFF},
1082 {0x22, 0xFF},
1083 {0x23, 0xFF},
1084 {0x24, 0xFF},
1085 {0x25, 0xFF},
1086 {0x26, 0xFF},
1087 {0x27, 0xFF},
1088 {0x28, 0xFF},
1089 {0x29, 0xFF},
1090 {0x2A, 0xFF},
1091 {0x2B, 0xFF},
1092 {0x2C, 0xFF},
1093 {0x2D, 0xFF},
1094 {0x2E, 0xFF},
1095 {0x2F, 0xFF},
1096 {0x30, 0xFF},
1097 {0x31, 0xFF},
1098 {0x32, 0xFF},
1099 {0x33, 0xFF},
1100 {0x34, 0xFF},
1101 // Page 1
1102 {0xfc, 0x01},
1103 {0x02, 0x02}, // YCbCr Order
1104 };
1105 #else
1106 #error No samsung CIS moudule !
1107 #endif
1108
1109
1110 // abridged VGA : 640 x 480
1111 s5k3xa_t s5k3aa_reg_vga[] =
1112 {
1113 /* Only for VGA Mode */
1114 {0xec,0x07}, //bpr by pyo
1115 {0x21,0x9c},
1116 {0x22,0x58},
1117 {0xec,0x00},
1118 {0x87,0x00},
1119 {0x86,0x48}, //bpr by pyo
1120
1121 {0xec,0x02},
1122 {0x02,0x0d}, //9bit
1123 {0x1f,0x07}, //global gain
1124
1125 {0xec,0x01},
1126 {0x21,0x40},
1127 {0x22,0x40},
1128 {0x23,0x00},
1129 {0x24,0x00},
1130
1131 {0xec,0x00},
1132 {0x7b,0x00},
1133 {0x73,0x51},
1134 {0x02,0x31}, //YONGKAL
1135 };
1136
1137 // abridged SXGA : 1280 x 1023 (1.3M)
1138 s5k3xa_t s5k3aa_reg_sxga[] =
1139 {
1140
1141 {0xec,0x07},
1142 {0x21,0x90},
1143 {0x22,0x60},
1144 {0xec,0x00},
1145 {0x87,0x00},
1146 {0x86,0x20},
1147
1148 {0xec,0x02},
1149 {0x02,0x0f},
1150 {0x1f,0x0f},
1151 {0xec,0x01},
1152 {0x21,0x50},
1153 {0x22,0x50},
1154 {0x23,0x10},
1155 {0x24,0x10},
1156 {0xec,0x00},
1157 {0x7b,0xff},
1158 {0x73,0x00},
1159 {0x02,0x00},
1160 };
1161
1162
1163 #define PAGE_ADDRESS 0xEC
1164
1165 #define S5K3AA_INIT_REGS (sizeof(s5k3aa_reg)/sizeof(s5k3aa_reg[0]))
1166 #define S5K3AA_SXGA_REGS (sizeof(s5k3aa_reg_sxga)/sizeof(s5k3aa_reg_sxga[0]))
1167 #define S5K3AA_VGA_REGS (sizeof(s5k3aa_reg_vga)/sizeof(s5k3aa_reg_vga[0]))
1168
1169 #define S5K3AA_RISC_REGS 0xEB
1170 #define S5K3AA_ISP_REGS 0xFB /* S5C7323X */
1171 #define S5K3AA_CIS_REGS 0x2F /* S5K437LA03 */
1172
1173 //#define S5K3AA_REGS (S5K3AA_RISC_REGS+S5K3AA_ISP_REGS+S5K3AA_CIS_REGS)
1174 #define S5K3AA_REGS (0x1000)
1175
1176 // For VGA ( 640 x 480) on 3BA module
1177 s5k3xa_t s5k3ba_reg_vga[] =
1178 {
1179 {0xfc, 0x01},
1180 {0x04, 0x03}, //ARM Clock divider(1/4)
1181
1182 //In case of PCLK = 64MHz
1183 {0xfc, 0x02},
1184 {0x52, 0x80}, //PLL M
1185
1186 {0xfc, 0x02},
1187 {0x50, 0x19}, //PLL S,P
1188
1189 {0xfc, 0x07},
1190 {0x58, 0x10},
1191 {0x59, 0x00},
1192 {0x5A, 0x00},
1193 {0x5B, 0x6c},
1194
1195 {0xfc, 0xf0},
1196 {0x00, 0x40},
1197
1198 {0xfc, 0x00},
1199 {0x62, 0x02},
1200 {0xbc, 0xe0}, // AWB_AE_DIFF, 0x03},
1201 {0x2d, 0x02},
1202 {0xfc, 0x01},
1203 {0x02, 0x02}, // YCbCr Order
1204
1205 {0xfc, 0x02},
1206 {0x4a, 0xc1}, // SC type selection
1207 {0x37, 0x18}, //16 // SC type global gain
1208 {0x47, 0xc4}, // r-ramp by chin
1209
1210
1211 {0xfc, 0x01}, //AWB Window Area (except sky)
1212 {0xc4, 0x01},
1213 {0xc5, 0x4e},
1214 {0xc7, 0x6e},
1215
1216 {0xfc, 0x02},
1217 {0x30, 0x84}, //Analog offset
1218
1219 {0xfc, 0x00},
1220 {0x3d, 0x10}, //AWB Low Y limit
1221
1222 {0xfc, 0x02},
1223 {0x3d, 0x06}, //ADLC OFF
1224 {0x44, 0x5b}, //clamp enable
1225 {0x55, 0x03},
1226
1227 {0xfc, 0x06},
1228 {0x0c, 0x01},
1229 {0x0d, 0x4e},
1230 {0x0f, 0x6e},
1231
1232 {0xfc, 0x00},
1233 {0x78, 0x58}, //AGC MAX (30lux_Micron灌扁Y=60code)
1234
1235 {0xfc, 0x02},
1236 {0x45, 0x8c}, //CDS timing_历炼档 greenish 秦搬(15fps)
1237 {0x49, 0x80}, // APS Current 2uA
1238
1239 {0xfc, 0x01},
1240 {0x25, 0x14}, //10 //Digital Clamp
1241
1242 {0xfc, 0x00},
1243 {0x6c, 0xac}, //AE target (Macbeth white=240)
1244 {0x6d, 0x00},
1245
1246 // 2. ISP tuning
1247 // ISP_tuning
1248 {0xfc, 0x00},
1249 {0x01, 0x00}, // I2C hold mode off
1250
1251 {0xfc, 0x01},
1252 {0x00, 0x00}, // ISP BPR Off
1253 {0x0c, 0x02}, // Full YC
1254 {0xc8, 0x19}, // AWB Y Max
1255
1256 {0xfc, 0x00},
1257 {0x81, 0x00}, // AWB G gain suppress disable
1258 {0x29, 0x04},
1259 {0x2a, 0x00},
1260 {0x2b, 0x04}, // color level
1261 {0x2c, 0x00},
1262
1263 {0xfc, 0x07},
1264 {0x11, 0x00}, // G offset
1265 {0x37, 0x00}, // Flicker Add
1266
1267 {0xfc, 0x00},
1268 {0x72, 0xa0}, // Flicker for 32MHz
1269 {0x74, 0x18}, // Flicker
1270 {0x73, 0x00}, // Frame AE
1271
1272 {0xfc, 0x05},
1273 {0x64, 0x00}, // Darkslice R
1274 {0x65, 0x00}, // Darkslice G
1275 {0x66, 0x00}, // Darkslice B
1276
1277 //Edge
1278 {0xfc, 0x05},
1279 {0x2c, 0x0a}, //14 // positive gain
1280 {0x30, 0x0a}, //10 // negative edge gain
1281 {0x34, 0x1a}, // APTCLP
1282 {0x35, 0x10}, //0a // APTSC
1283 {0x36, 0x0b}, // ENHANCE
1284 {0x3f, 0x00}, // NON-LIN
1285 {0x45, 0x30}, // EGREF
1286 {0x47, 0x00}, // LLREF
1287 {0x48, 0x08}, // by chin
1288 {0x49, 0x39}, // CSSEL EGSEL CS_DLY by
1289 {0x40, 0x41}, // Y delay
1290
1291 {0xfc, 0x00},
1292 {0x7e, 0xfc},
1293 // s7e8c //NR GrGb off
1294 // [7]: BPR [6]:Noise Filter(1D/NR) [4]: GrGb Enable [3]:BPR Data Threshold
1295 // [2]: color suppress [1]: Y gain suppress [0]: Digital Clamp
1296
1297 // GrGb Correction setting
1298 {0xfc, 0x01},
1299 {0x44, 0x0c},
1300 //s4400
1301 /// [4]: GrGb full [3]: GrGb On
1302 /// [2]: GrGb Rb On
1303 {0xfc, 0x0b},
1304 {0x21, 0x00}, // Start AGC
1305 {0x22, 0x10}, // AGCMIN
1306 {0x23, 0x50}, // AGCMAX
1307 {0x24, 0x18}, // G Th AGCMIN(23d)
1308 {0x25, 0x52}, // G Th AGCMAX(50d)
1309 {0x26, 0x38}, // RB Th AGCMIN
1310 {0x27, 0x52}, // RB Th AGCMAX
1311 // GrGb Correction setting End
1312
1313 ///////////////////////////////////
1314 // BPR Setting
1315 {0xfc, 0x01},
1316 {0x3f, 0x00}, // setting because S/W bug
1317
1318 {0xfc, 0x0b},
1319 {0x0b, 0x00}, // ISP BPR On Start
1320 {0x0c, 0x00}, // Th13 AGC Min
1321 {0x0d, 0x5a}, // Th13 AGC Max
1322 {0x0e, 0x01}, //00 // Th1 Max H for AGCMIN
1323 {0x0f, 0xff}, //c0 // Th1 Max L for AGCMIN
1324 {0x10, 0x00}, // Th1 Min H for AGCMAX
1325 {0x11, 0x10}, //00 // Th1 Min L for AGCMAX
1326 {0x12, 0xff}, // Th3 Max H for AGCMIN
1327 {0x13, 0xff}, // Th3 Max L for AGCMIN
1328 {0x14, 0xff}, // Th3 Min H for AGCMAX
1329 {0x15, 0xff}, // Th3 Min L for AGCMAX
1330
1331 // NR Setting
1332 {0xfc, 0x01},
1333 {0x4b, 0x01}, // NR Enable
1334 // s4b00 // NR Enable
1335
1336 {0xfc, 0x0b},
1337 {0x28, 0x00}, //NR Start AGC
1338 {0x29, 0x00}, // SIG Th AGCMIN H
1339 {0x2a, 0x0a}, //14 // SIG Th AGCMIN L
1340 {0x2b, 0x00}, // SIG Th AGCMAX H
1341 {0x2c, 0x0a}, //14 // SIG Th AGCMAX L
1342 {0x2d, 0x00}, // PRE Th AGCMIN H
1343 {0x2e, 0xc0}, //64 // PRE Th AGCMIN L(100d)
1344 {0x2f, 0x01}, // PRE Th AGCMAX H(300d)
1345 {0x30, 0x2c}, // PRE Th AGCMAX L
1346 {0x31, 0x00}, // POST Th AGCMIN H
1347 {0x32, 0xe0}, //64 // POST Th AGCMIN L(100d)
1348 {0x33, 0x01}, // POST Th AGCMAX H(300d)
1349 {0x34, 0x2c}, // POST Th AGCMAX L
1350 // NR Setting End
1351
1352 // Color suppress setting
1353 {0xfc, 0x0b},
1354 {0x08, 0x50}, // C suppress AGC MIN
1355 {0x09, 0x03}, // C suppress MIN H
1356 {0x0a, 0x80}, // C suppress MIN L
1357 // C Suppress Setting End
1358
1359 {0xfc, 0x05},
1360 {0x4a, 0x00}, //01 // Edge Color Suppress, 9/13
1361
1362 // 1D Y LPF Filter
1363 {0xfc, 0x01},
1364 // s05e0 // Default s60
1365 {0x05, 0x60}, // Default s60
1366 // [7]: Y LPF filter On [6]: Clap On
1367
1368 {0xfc, 0x0b},
1369 {0x35, 0x00}, // YLPF Start AGC
1370 {0x36, 0x50}, // YLPF01 AGCMIN
1371 {0x37, 0x50}, // YLPF01 AGCMAX
1372 {0x38, 0x00}, // YLPF SIG01 Th AGCMINH
1373 {0x39, 0x90}, //00 // YLPF SIG01 Th AGCMINL
1374 {0x3a, 0x01}, // YLPF SIG01 Th AGCMAXH
1375 {0x3b, 0xa0}, // YLPF SIG01 Th AGCMAXL
1376 {0x3c, 0x50}, // YLPF02 AGCMIN
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