module.fit.eqn

前级放大和AD转换的完整程序的可是图

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--current_state.st0 is current_state.st0 at LC_X2_Y26_N4
--operation mode is normal

current_state.st0_lut_out = !current_state.st4 # !rdy # !int;
current_state.st0 = DFFEAS(current_state.st0_lut_out, GLOBAL(CLK), VCC, , , , , , );


--current_state.st1 is current_state.st1 at LC_X2_Y26_N2
--operation mode is normal

current_state.st1_lut_out = current_state.st1 & (rdy # !int) # !current_state.st0;
current_state.st1 = DFFEAS(current_state.st1_lut_out, GLOBAL(CLK), VCC, , , , , , );


--A1L29 is RD~0 at LC_X2_Y26_N8
--operation mode is normal

A1L29 = current_state.st1 # !current_state.st0;


--REGL[0] is REGL[0] at LC_X1_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[0]_lut_out = GND;
REGL[0] = DFFEAS(REGL[0]_lut_out, GLOBAL(int), VCC, , , d[0], , , VCC);


--REGL[1] is REGL[1] at LC_X12_Y26_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[1]_lut_out = GND;
REGL[1] = DFFEAS(REGL[1]_lut_out, GLOBAL(int), VCC, , , d[1], , , VCC);


--REGL[2] is REGL[2] at LC_X52_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[2]_lut_out = GND;
REGL[2] = DFFEAS(REGL[2]_lut_out, GLOBAL(int), VCC, , , d[2], , , VCC);


--REGL[3] is REGL[3] at LC_X52_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[3]_lut_out = GND;
REGL[3] = DFFEAS(REGL[3]_lut_out, GLOBAL(int), VCC, , , d[3], , , VCC);


--REGL[4] is REGL[4] at LC_X14_Y1_N2
--operation mode is normal

REGL[4]_lut_out = d[4];
REGL[4] = DFFEAS(REGL[4]_lut_out, GLOBAL(int), VCC, , , , , , );


--REGL[5] is REGL[5] at LC_X46_Y1_N2
--operation mode is normal

REGL[5]_lut_out = d[5];
REGL[5] = DFFEAS(REGL[5]_lut_out, GLOBAL(int), VCC, , , , , , );


--REGL[6] is REGL[6] at LC_X48_Y26_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[6]_lut_out = GND;
REGL[6] = DFFEAS(REGL[6]_lut_out, GLOBAL(int), VCC, , , d[6], , , VCC);


--REGL[7] is REGL[7] at LC_X10_Y26_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[7]_lut_out = GND;
REGL[7] = DFFEAS(REGL[7]_lut_out, GLOBAL(int), VCC, , , d[7], , , VCC);


--current_state.st4 is current_state.st4 at LC_X2_Y26_N5
--operation mode is normal

current_state.st4_lut_out = rdy & !int & (current_state.st3 # current_state.st4) # !rdy & (current_state.st4);
current_state.st4 = DFFEAS(current_state.st4_lut_out, GLOBAL(CLK), VCC, , , , , , );


--current_state.st3 is current_state.st3 at LC_X2_Y26_N9
--operation mode is normal

current_state.st3_lut_out = int & (current_state.st3 # !rdy & current_state.st2) # !int & !rdy & current_state.st3;
current_state.st3 = DFFEAS(current_state.st3_lut_out, GLOBAL(CLK), VCC, , , , , , );


--current_state.st2 is current_state.st2 at LC_X2_Y26_N6
--operation mode is normal

current_state.st2_lut_out = int & (rdy & (current_state.st2) # !rdy & current_state.st1) # !int & (current_state.st2);
current_state.st2 = DFFEAS(current_state.st2_lut_out, GLOBAL(CLK), VCC, , , , , , );


--st is st at PIN_66
--operation mode is input

st = INPUT();


--rdy is rdy at PIN_240
--operation mode is input

rdy = INPUT();


--int is int at PIN_29
--operation mode is input

int = INPUT();


--CLK is CLK at PIN_28
--operation mode is input

CLK = INPUT();


--d[0] is d[0] at PIN_38
--operation mode is input

d[0] = INPUT();


--d[1] is d[1] at PIN_223
--operation mode is input

d[1] = INPUT();


--d[2] is d[2] at PIN_143
--operation mode is input

d[2] = INPUT();


--d[3] is d[3] at PIN_141
--operation mode is input

d[3] = INPUT();


--d[4] is d[4] at PIN_83
--operation mode is input

d[4] = INPUT();


--d[5] is d[5] at PIN_107
--operation mode is input

d[5] = INPUT();


--d[6] is d[6] at PIN_187
--operation mode is input

d[6] = INPUT();


--d[7] is d[7] at PIN_226
--operation mode is input

d[7] = INPUT();


--CS is CS at PIN_2
--operation mode is output

CS = OUTPUT(!current_state.st0);


--RD is RD at PIN_239
--operation mode is output

RD = OUTPUT(A1L29);


--Q[0] is Q[0] at PIN_39
--operation mode is output

Q[0] = OUTPUT(REGL[0]);


--Q[1] is Q[1] at PIN_222
--operation mode is output

Q[1] = OUTPUT(REGL[1]);


--Q[2] is Q[2] at PIN_144
--operation mode is output

Q[2] = OUTPUT(REGL[2]);


--Q[3] is Q[3] at PIN_140
--operation mode is output

Q[3] = OUTPUT(REGL[3]);


--Q[4] is Q[4] at PIN_82
--operation mode is output

Q[4] = OUTPUT(REGL[4]);


--Q[5] is Q[5] at PIN_108
--operation mode is output

Q[5] = OUTPUT(REGL[5]);


--Q[6] is Q[6] at PIN_186
--operation mode is output

Q[6] = OUTPUT(REGL[6]);


--Q[7] is Q[7] at PIN_224
--operation mode is output

Q[7] = OUTPUT(REGL[7]);