module.map.eqn

前级放大和AD转换的完整程序的可是图

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--current_state.st0 is current_state.st0
--operation mode is normal

current_state.st0_lut_out = !int # !rdy # !current_state.st4;
current_state.st0 = DFFEAS(current_state.st0_lut_out, CLK, VCC, , , , , , );


--current_state.st1 is current_state.st1
--operation mode is normal

current_state.st1_lut_out = current_state.st1 & (rdy # !int) # !current_state.st0;
current_state.st1 = DFFEAS(current_state.st1_lut_out, CLK, VCC, , , , , , );


--A1L29 is RD~0
--operation mode is normal

A1L29 = current_state.st1 # !current_state.st0;


--REGL[0] is REGL[0]
--operation mode is normal

REGL[0]_lut_out = d[0];
REGL[0] = DFFEAS(REGL[0]_lut_out, int, VCC, , , , , , );


--REGL[1] is REGL[1]
--operation mode is normal

REGL[1]_lut_out = d[1];
REGL[1] = DFFEAS(REGL[1]_lut_out, int, VCC, , , , , , );


--REGL[2] is REGL[2]
--operation mode is normal

REGL[2]_lut_out = d[2];
REGL[2] = DFFEAS(REGL[2]_lut_out, int, VCC, , , , , , );


--REGL[3] is REGL[3]
--operation mode is normal

REGL[3]_lut_out = d[3];
REGL[3] = DFFEAS(REGL[3]_lut_out, int, VCC, , , , , , );


--REGL[4] is REGL[4]
--operation mode is normal

REGL[4]_lut_out = d[4];
REGL[4] = DFFEAS(REGL[4]_lut_out, int, VCC, , , , , , );


--REGL[5] is REGL[5]
--operation mode is normal

REGL[5]_lut_out = d[5];
REGL[5] = DFFEAS(REGL[5]_lut_out, int, VCC, , , , , , );


--REGL[6] is REGL[6]
--operation mode is normal

REGL[6]_lut_out = d[6];
REGL[6] = DFFEAS(REGL[6]_lut_out, int, VCC, , , , , , );


--REGL[7] is REGL[7]
--operation mode is normal

REGL[7]_lut_out = d[7];
REGL[7] = DFFEAS(REGL[7]_lut_out, int, VCC, , , , , , );


--current_state.st4 is current_state.st4
--operation mode is normal

current_state.st4_lut_out = rdy & !int & (current_state.st4 # current_state.st3) # !rdy & current_state.st4;
current_state.st4 = DFFEAS(current_state.st4_lut_out, CLK, VCC, , , , , , );


--current_state.st3 is current_state.st3
--operation mode is normal

current_state.st3_lut_out = current_state.st3 & (int # !rdy) # !current_state.st3 & int & current_state.st2 & !rdy;
current_state.st3 = DFFEAS(current_state.st3_lut_out, CLK, VCC, , , , , , );


--current_state.st2 is current_state.st2
--operation mode is normal

current_state.st2_lut_out = int & (rdy & current_state.st2 # !rdy & (current_state.st1)) # !int & current_state.st2;
current_state.st2 = DFFEAS(current_state.st2_lut_out, CLK, VCC, , , , , , );


--st is st
--operation mode is input

st = INPUT();


--rdy is rdy
--operation mode is input

rdy = INPUT();


--int is int
--operation mode is input

int = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--d[0] is d[0]
--operation mode is input

d[0] = INPUT();


--d[1] is d[1]
--operation mode is input

d[1] = INPUT();


--d[2] is d[2]
--operation mode is input

d[2] = INPUT();


--d[3] is d[3]
--operation mode is input

d[3] = INPUT();


--d[4] is d[4]
--operation mode is input

d[4] = INPUT();


--d[5] is d[5]
--operation mode is input

d[5] = INPUT();


--d[6] is d[6]
--operation mode is input

d[6] = INPUT();


--d[7] is d[7]
--operation mode is input

d[7] = INPUT();


--CS is CS
--operation mode is output

CS = OUTPUT(!current_state.st0);


--RD is RD
--operation mode is output

RD = OUTPUT(A1L29);


--Q[0] is Q[0]
--operation mode is output

Q[0] = OUTPUT(REGL[0]);


--Q[1] is Q[1]
--operation mode is output

Q[1] = OUTPUT(REGL[1]);


--Q[2] is Q[2]
--operation mode is output

Q[2] = OUTPUT(REGL[2]);


--Q[3] is Q[3]
--operation mode is output

Q[3] = OUTPUT(REGL[3]);


--Q[4] is Q[4]
--operation mode is output

Q[4] = OUTPUT(REGL[4]);


--Q[5] is Q[5]
--operation mode is output

Q[5] = OUTPUT(REGL[5]);


--Q[6] is Q[6]
--operation mode is output

Q[6] = OUTPUT(REGL[6]);


--Q[7] is Q[7]
--operation mode is output

Q[7] = OUTPUT(REGL[7]);