module.tan.qmsg

前级放大和AD转换的完整程序的可是图

{ "Info" "ITDB_TH_RESULT" "current_state.st1 int CLK -0.174 ns register " "Info: th for register \"current_state.st1\" (data pin = \"int\", clock pin = \"CLK\") is -0.174 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.245 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { CLK } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns current_state.st1 2 REG LC_X2_Y26_N2 3 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.776 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.434 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.434 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns int 1 CLK PIN_29 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 13; CLK Node = 'int'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { int } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.656 ns) + CELL(0.309 ns) 3.434 ns current_state.st1 2 REG LC_X2_Y26_N2 3 " "Info: 2: + IC(1.656 ns) + CELL(0.309 ns) = 3.434 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.965 ns" { int current_state.st1 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 51.78 % ) " "Info: Total cell delay = 1.778 ns ( 51.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.656 ns ( 48.22 % ) " "Info: Total interconnect delay = 1.656 ns ( 48.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.434 ns" { int current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.434 ns" { int int~out0 current_state.st1 } { 0.000ns 0.000ns 1.656ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.434 ns" { int current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.434 ns" { int int~out0 current_state.st1 } { 0.000ns 0.000ns 1.656ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 15 20:48:56 2008 " "Info: Processing ended: Thu May 15 20:48:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}