module.tan.qmsg

前级放大和AD转换的完整程序的可是图

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register current_state.st1 current_state.st1 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"current_state.st1\" and destination register \"current_state.st1\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.291 ns + Longest register register " "Info: + Longest register to register delay is 1.291 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st1 1 REG LC_X2_Y26_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { current_state.st1 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.738 ns) 1.291 ns current_state.st1 2 REG LC_X2_Y26_N2 3 " "Info: 2: + IC(0.553 ns) + CELL(0.738 ns) = 1.291 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.291 ns" { current_state.st1 current_state.st1 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 57.16 % ) " "Info: Total cell delay = 0.738 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 42.84 % ) " "Info: Total interconnect delay = 0.553 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.291 ns" { current_state.st1 current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.291 ns" { current_state.st1 current_state.st1 } { 0.000ns 0.553ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.245 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { CLK } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns current_state.st1 2 REG LC_X2_Y26_N2 3 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.776 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.245 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { CLK } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns current_state.st1 2 REG LC_X2_Y26_N2 3 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.776 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.291 ns" { current_state.st1 current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.291 ns" { current_state.st1 current_state.st1 } { 0.000ns 0.553ns } { 0.000ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { current_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { current_state.st1 } {  } {  } } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "int " "Info: No valid register-to-register data paths exist for clock \"int\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st4 rdy CLK 3.970 ns register " "Info: tsu for register \"current_state.st4\" (data pin = \"rdy\", clock pin = \"CLK\") is 3.970 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.178 ns + Longest pin register " "Info: + Longest pin to register delay is 7.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rdy 1 PIN PIN_240 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 5; PIN Node = 'rdy'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { rdy } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.096 ns) + CELL(0.607 ns) 7.178 ns current_state.st4 2 REG LC_X2_Y26_N5 2 " "Info: 2: + IC(5.096 ns) + CELL(0.607 ns) = 7.178 ns; Loc. = LC_X2_Y26_N5; Fanout = 2; REG Node = 'current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "5.703 ns" { rdy current_state.st4 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 29.01 % ) " "Info: Total cell delay = 2.082 ns ( 29.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.096 ns ( 70.99 % ) " "Info: Total interconnect delay = 5.096 ns ( 70.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "7.178 ns" { rdy current_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.178 ns" { rdy rdy~out0 current_state.st4 } { 0.000ns 0.000ns 5.096ns } { 0.000ns 1.475ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.245 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { CLK } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns current_state.st4 2 REG LC_X2_Y26_N5 2 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N5; Fanout = 2; REG Node = 'current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.776 ns" { CLK current_state.st4 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st4 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "7.178 ns" { rdy current_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.178 ns" { rdy rdy~out0 current_state.st4 } { 0.000ns 0.000ns 5.096ns } { 0.000ns 1.475ns 0.607ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st4 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK RD current_state.st0 7.778 ns register " "Info: tco from clock \"CLK\" to destination pin \"RD\" through register \"current_state.st0\" is 7.778 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.245 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { CLK } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns current_state.st0 2 REG LC_X2_Y26_N4 3 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N4; Fanout = 3; REG Node = 'current_state.st0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "1.776 ns" { CLK current_state.st0 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.309 ns + Longest register pin " "Info: + Longest register to pin delay is 4.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st0 1 REG LC_X2_Y26_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y26_N4; Fanout = 3; REG Node = 'current_state.st0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { current_state.st0 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.442 ns) 0.956 ns RD~0 2 COMB LC_X2_Y26_N8 1 " "Info: 2: + IC(0.514 ns) + CELL(0.442 ns) = 0.956 ns; Loc. = LC_X2_Y26_N8; Fanout = 1; COMB Node = 'RD~0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "0.956 ns" { current_state.st0 RD~0 } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(2.108 ns) 4.309 ns RD 3 PIN PIN_239 0 " "Info: 3: + IC(1.245 ns) + CELL(2.108 ns) = 4.309 ns; Loc. = PIN_239; Fanout = 0; PIN Node = 'RD'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.353 ns" { RD~0 RD } "NODE_NAME" } "" } } { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.550 ns ( 59.18 % ) " "Info: Total cell delay = 2.550 ns ( 59.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.759 ns ( 40.82 % ) " "Info: Total interconnect delay = 1.759 ns ( 40.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "4.309 ns" { current_state.st0 RD~0 RD } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.309 ns" { current_state.st0 RD~0 RD } { 0.000ns 0.514ns 1.245ns } { 0.000ns 0.442ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "3.245 ns" { CLK current_state.st0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK CLK~out0 current_state.st0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "4.309 ns" { current_state.st0 RD~0 RD } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.309 ns" { current_state.st0 RD~0 RD } { 0.000ns 0.514ns 1.245ns } { 0.000ns 0.442ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}