module.fit.qmsg

前级放大和AD转换的完整程序的可是图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 15 20:48:43 2008 " "Info: Processing started: Thu May 15 20:48:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off module -c module " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off module -c module" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "module EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"module\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "22 22 " "Info: No exact pin location assignment(s) for 22 pins of 22 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "st " "Info: Pin st not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "st" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { st } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { st } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CS " "Info: Pin CS not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CS" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { CS } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { CS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "RD " "Info: Pin RD not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 10 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RD" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { RD } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { RD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[0\] " "Info: Pin Q\[0\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[0] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[1\] " "Info: Pin Q\[1\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[1] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[2\] " "Info: Pin Q\[2\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[2] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[3\] " "Info: Pin Q\[3\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[3] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[4\] " "Info: Pin Q\[4\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[4] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[5\] " "Info: Pin Q\[5\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[5] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[6\] " "Info: Pin Q\[6\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[6] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[7\] " "Info: Pin Q\[7\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Q\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { Q[7] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { Q[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rdy " "Info: Pin rdy not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 6 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rdy" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { rdy } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { rdy } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "int " "Info: Pin int not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 7 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "int" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { int } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { int } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 5 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { CLK } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[0\] " "Info: Pin d\[0\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[0] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[1\] " "Info: Pin d\[1\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[1] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[2\] " "Info: Pin d\[2\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[2] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[3\] " "Info: Pin d\[3\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[3] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[4\] " "Info: Pin d\[4\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[4] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[5\] " "Info: Pin d\[5\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[5] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[6\] " "Info: Pin d\[6\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[6] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[7\] " "Info: Pin d\[7\] not assigned to an exact location on the device" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 4 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "module" "UNKNOWN" "V1" "E:/vhdl code/module/db/module.quartus_db" { Floorplan "E:/vhdl code/module/" "" "" { d[7] } "NODE_NAME" } "" } } { "E:/vhdl code/module/module.fld" "" { Floorplan "E:/vhdl code/module/module.fld" "" "" { d[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "int Global clock in PIN 29 " "Info: Automatically promoted some destinations of signal \"int\" to use Global clock in PIN 29" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "current_state.st0 " "Info: Destination \"current_state.st0\" may be non-global or may not use global clock" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "current_state.st1 " "Info: Destination \"current_state.st1\" may be non-global or may not use global clock" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "current_state.st4 " "Info: Destination \"current_state.st4\" may be non-global or may not use global clock" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "current_state.st3 " "Info: Destination \"current_state.st3\" may be non-global or may not use global clock" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "current_state.st2 " "Info: Destination \"current_state.st2\" may be non-global or may not use global clock" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 28 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN 28" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 5 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}