module.map.qmsg

前级放大和AD转换的完整程序的可是图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 15 20:48:39 2008 " "Info: Processing started: Thu May 15 20:48:39 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off module -c module " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off module -c module" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "module.vhd 2 1 " "Warning: Using design file module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 module-behav " "Info: Found design unit 1: module-behav" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 module " "Info: Found entity 1: module" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "module " "Info: Elaborating entity \"module\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "LOCK module.vhd(17) " "Info (10035): Verilog HDL or VHDL information at module.vhd(17): object \"LOCK\" declared but not used" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 17 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "module.vhd(41) " "Info (10425): VHDL Case Statement information at module.vhd(41): OTHERS choice is never selected" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 41 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|module\|current_state 5 " "Info: State machine \"\|module\|current_state\" contains 5 states" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|module\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|module\|current_state\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|module\|current_state " "Info: Encoding result for state machine \"\|module\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st4 " "Info: Encoded state bit \"current_state.st4\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st3 " "Info: Encoded state bit \"current_state.st3\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st2 " "Info: Encoded state bit \"current_state.st2\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st1 " "Info: Encoded state bit \"current_state.st1\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st0 " "Info: Encoded state bit \"current_state.st0\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|module\|current_state.st0 00000 " "Info: State \"\|module\|current_state.st0\" uses code string \"00000\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|module\|current_state.st1 00011 " "Info: State \"\|module\|current_state.st1\" uses code string \"00011\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|module\|current_state.st2 00101 " "Info: State \"\|module\|current_state.st2\" uses code string \"00101\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|module\|current_state.st3 01001 " "Info: State \"\|module\|current_state.st3\" uses code string \"01001\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|module\|current_state.st4 10001 " "Info: State \"\|module\|current_state.st4\" uses code string \"10001\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 22 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "st " "Warning: No output dependent on input pin \"st\"" {  } { { "module.vhd" "" { Text "E:/vhdl code/module/module.vhd" 8 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "36 " "Info: Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 15 20:48:41 2008 " "Info: Processing ended: Thu May 15 20:48:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}