module.tan.rpt

前级放大和AD转换的完整程序的可是图

; N/A   ; None         ; 0.655 ns   ; int  ; current_state.st3 ; CLK      ;
; N/A   ; None         ; 0.226 ns   ; int  ; current_state.st1 ; CLK      ;
+-------+--------------+------------+------+-------------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+-------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To   ; From Clock ;
+-------+--------------+------------+-------------------+------+------------+
; N/A   ; None         ; 7.778 ns   ; current_state.st0 ; RD   ; CLK        ;
; N/A   ; None         ; 7.687 ns   ; current_state.st1 ; RD   ; CLK        ;
; N/A   ; None         ; 7.001 ns   ; current_state.st0 ; CS   ; CLK        ;
; N/A   ; None         ; 6.878 ns   ; REGL[1]           ; Q[1] ; int        ;
; N/A   ; None         ; 6.875 ns   ; REGL[7]           ; Q[7] ; int        ;
; N/A   ; None         ; 6.812 ns   ; REGL[6]           ; Q[6] ; int        ;
; N/A   ; None         ; 6.796 ns   ; REGL[4]           ; Q[4] ; int        ;
; N/A   ; None         ; 6.735 ns   ; REGL[5]           ; Q[5] ; int        ;
; N/A   ; None         ; 6.662 ns   ; REGL[0]           ; Q[0] ; int        ;
; N/A   ; None         ; 6.600 ns   ; REGL[3]           ; Q[3] ; int        ;
; N/A   ; None         ; 6.599 ns   ; REGL[2]           ; Q[2] ; int        ;
+-------+--------------+------------+-------------------+------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; -0.174 ns ; int  ; current_state.st1 ; CLK      ;
; N/A           ; None        ; -0.603 ns ; int  ; current_state.st3 ; CLK      ;
; N/A           ; None        ; -0.604 ns ; int  ; current_state.st0 ; CLK      ;
; N/A           ; None        ; -0.606 ns ; int  ; current_state.st2 ; CLK      ;
; N/A           ; None        ; -0.607 ns ; int  ; current_state.st4 ; CLK      ;
; N/A           ; None        ; -2.970 ns ; d[0] ; REGL[0]           ; int      ;
; N/A           ; None        ; -3.022 ns ; d[2] ; REGL[2]           ; int      ;
; N/A           ; None        ; -3.029 ns ; d[3] ; REGL[3]           ; int      ;
; N/A           ; None        ; -3.350 ns ; d[7] ; REGL[7]           ; int      ;
; N/A           ; None        ; -3.350 ns ; d[1] ; REGL[1]           ; int      ;
; N/A           ; None        ; -3.418 ns ; d[6] ; REGL[6]           ; int      ;
; N/A           ; None        ; -3.602 ns ; d[4] ; REGL[4]           ; int      ;
; N/A           ; None        ; -3.661 ns ; d[5] ; REGL[5]           ; int      ;
; N/A           ; None        ; -3.909 ns ; rdy  ; current_state.st1 ; CLK      ;
; N/A           ; None        ; -3.913 ns ; rdy  ; current_state.st0 ; CLK      ;
; N/A           ; None        ; -3.914 ns ; rdy  ; current_state.st3 ; CLK      ;
; N/A           ; None        ; -3.917 ns ; rdy  ; current_state.st2 ; CLK      ;
; N/A           ; None        ; -3.918 ns ; rdy  ; current_state.st4 ; CLK      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu May 15 20:48:55 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off module -c module --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "int" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "current_state.st1" and destination register "current_state.st1"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.291 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'
            Info: 2: + IC(0.553 ns) + CELL(0.738 ns) = 1.291 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'
            Info: Total cell delay = 0.738 ns ( 57.16 % )
            Info: Total interconnect delay = 0.553 ns ( 42.84 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 3.245 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'
                Info: Total cell delay = 2.180 ns ( 67.18 % )
                Info: Total interconnect delay = 1.065 ns ( 32.82 % )
            Info: - Longest clock path from clock "CLK" to source register is 3.245 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'
                Info: Total cell delay = 2.180 ns ( 67.18 % )
                Info: Total interconnect delay = 1.065 ns ( 32.82 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: No valid register-to-register data paths exist for clock "int"
Info: tsu for register "current_state.st4" (data pin = "rdy", clock pin = "CLK") is 3.970 ns
    Info: + Longest pin to register delay is 7.178 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 5; PIN Node = 'rdy'
        Info: 2: + IC(5.096 ns) + CELL(0.607 ns) = 7.178 ns; Loc. = LC_X2_Y26_N5; Fanout = 2; REG Node = 'current_state.st4'
        Info: Total cell delay = 2.082 ns ( 29.01 % )
        Info: Total interconnect delay = 5.096 ns ( 70.99 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.245 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N5; Fanout = 2; REG Node = 'current_state.st4'
        Info: Total cell delay = 2.180 ns ( 67.18 % )
        Info: Total interconnect delay = 1.065 ns ( 32.82 % )
Info: tco from clock "CLK" to destination pin "RD" through register "current_state.st0" is 7.778 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.245 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N4; Fanout = 3; REG Node = 'current_state.st0'
        Info: Total cell delay = 2.180 ns ( 67.18 % )
        Info: Total interconnect delay = 1.065 ns ( 32.82 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.309 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y26_N4; Fanout = 3; REG Node = 'current_state.st0'
        Info: 2: + IC(0.514 ns) + CELL(0.442 ns) = 0.956 ns; Loc. = LC_X2_Y26_N8; Fanout = 1; COMB Node = 'RD~0'
        Info: 3: + IC(1.245 ns) + CELL(2.108 ns) = 4.309 ns; Loc. = PIN_239; Fanout = 0; PIN Node = 'RD'
        Info: Total cell delay = 2.550 ns ( 59.18 % )
        Info: Total interconnect delay = 1.759 ns ( 40.82 % )
Info: th for register "current_state.st1" (data pin = "int", clock pin = "CLK") is -0.174 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.245 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'
        Info: Total cell delay = 2.180 ns ( 67.18 % )
        Info: Total interconnect delay = 1.065 ns ( 32.82 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.434 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 13; CLK Node = 'int'
        Info: 2: + IC(1.656 ns) + CELL(0.309 ns) = 3.434 ns; Loc. = LC_X2_Y26_N2; Fanout = 3; REG Node = 'current_state.st1'
        Info: Total cell delay = 1.778 ns ( 51.78 % )
        Info: Total interconnect delay = 1.656 ns ( 48.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 15 20:48:56 2008
    Info: Elapsed time: 00:00:02