module.tan.rpt

前级放大和AD转换的完整程序的可是图

Timing Analyzer report for module
Thu May 15 20:48:56 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                              ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From              ; To                ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.970 ns                                       ; rdy               ; current_state.st4 ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.778 ns                                       ; current_state.st0 ; RD                ; CLK        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.174 ns                                      ; int               ; current_state.st1 ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st1 ; current_state.st1 ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                   ;                   ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; int             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                         ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From              ; To                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st1 ; current_state.st1 ; CLK        ; CLK      ; None                        ; None                      ; 1.291 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st1 ; current_state.st2 ; CLK        ; CLK      ; None                        ; None                      ; 1.052 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st3 ; current_state.st4 ; CLK        ; CLK      ; None                        ; None                      ; 1.044 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st3 ; current_state.st3 ; CLK        ; CLK      ; None                        ; None                      ; 1.043 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st0 ; current_state.st1 ; CLK        ; CLK      ; None                        ; None                      ; 1.029 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st4 ; current_state.st0 ; CLK        ; CLK      ; None                        ; None                      ; 0.841 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st2 ; current_state.st3 ; CLK        ; CLK      ; None                        ; None                      ; 0.840 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st2 ; current_state.st2 ; CLK        ; CLK      ; None                        ; None                      ; 0.838 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st4 ; current_state.st4 ; CLK        ; CLK      ; None                        ; None                      ; 0.837 ns                ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tsu                                                                     ;
+-------+--------------+------------+------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To                ; To Clock ;
+-------+--------------+------------+------+-------------------+----------+
; N/A   ; None         ; 3.970 ns   ; rdy  ; current_state.st4 ; CLK      ;
; N/A   ; None         ; 3.969 ns   ; rdy  ; current_state.st2 ; CLK      ;
; N/A   ; None         ; 3.966 ns   ; rdy  ; current_state.st3 ; CLK      ;
; N/A   ; None         ; 3.965 ns   ; rdy  ; current_state.st0 ; CLK      ;
; N/A   ; None         ; 3.961 ns   ; rdy  ; current_state.st1 ; CLK      ;
; N/A   ; None         ; 3.713 ns   ; d[5] ; REGL[5]           ; int      ;
; N/A   ; None         ; 3.654 ns   ; d[4] ; REGL[4]           ; int      ;
; N/A   ; None         ; 3.470 ns   ; d[6] ; REGL[6]           ; int      ;
; N/A   ; None         ; 3.402 ns   ; d[7] ; REGL[7]           ; int      ;
; N/A   ; None         ; 3.402 ns   ; d[1] ; REGL[1]           ; int      ;
; N/A   ; None         ; 3.081 ns   ; d[3] ; REGL[3]           ; int      ;
; N/A   ; None         ; 3.074 ns   ; d[2] ; REGL[2]           ; int      ;
; N/A   ; None         ; 3.022 ns   ; d[0] ; REGL[0]           ; int      ;
; N/A   ; None         ; 0.659 ns   ; int  ; current_state.st4 ; CLK      ;
; N/A   ; None         ; 0.658 ns   ; int  ; current_state.st2 ; CLK      ;
; N/A   ; None         ; 0.656 ns   ; int  ; current_state.st0 ; CLK      ;