module.map.rpt

前级放大和AD转换的完整程序的可是图

+----------------------------------+-----------------+-----------+--------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 14    ;
;     -- Combinational with no register       ; 1     ;
;     -- Register only                        ; 8     ;
;     -- Combinational with a register        ; 5     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 4     ;
;     -- 3 input functions                    ; 1     ;
;     -- 2 input functions                    ; 1     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 14    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 13    ;
; I/O pins                                    ; 22    ;
; Maximum fan-out node                        ; int   ;
; Maximum fan-out                             ; 13    ;
; Total fan-out                               ; 52    ;
; Average fan-out                             ; 1.44  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |module                    ; 14 (14)     ; 13           ; 0           ; 22   ; 0            ; 1 (1)        ; 8 (8)             ; 5 (5)            ; 0 (0)           ; 0 (0)      ; |module             ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |module|current_state                                                                                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; current_state.st4 ; current_state.st3 ; current_state.st2 ; current_state.st1 ; current_state.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; current_state.st0 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; current_state.st1 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; current_state.st2 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; current_state.st3 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; current_state.st4 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 13    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/vhdl code/module/module.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu May 15 20:48:39 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off module -c module
Warning: Using design file module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: module-behav
    Info: Found entity 1: module
Info: Elaborating entity "module" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at module.vhd(17): object "LOCK" declared but not used
Info (10425): VHDL Case Statement information at module.vhd(41): OTHERS choice is never selected
Info: State machine "|module|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|module|current_state"
Info: Encoding result for state machine "|module|current_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "current_state.st4"
        Info: Encoded state bit "current_state.st3"
        Info: Encoded state bit "current_state.st2"
        Info: Encoded state bit "current_state.st1"
        Info: Encoded state bit "current_state.st0"
    Info: State "|module|current_state.st0" uses code string "00000"
    Info: State "|module|current_state.st1" uses code string "00011"
    Info: State "|module|current_state.st2" uses code string "00101"
    Info: State "|module|current_state.st3" uses code string "01001"
    Info: State "|module|current_state.st4" uses code string "10001"
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "st"
Info: Implemented 36 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 10 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu May 15 20:48:41 2008
    Info: Elapsed time: 00:00:02