module.vhd

来自「前级放大和AD转换的完整程序的可是图」· VHDL 代码 · 共 48 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY module IS
   PORT(d  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  --来自0809转换好的8位数据
CLK  : IN STD_LOGIC;                    --状态机工作时钟
rdy  : IN STD_LOGIC;           --转换状态指示，低电平表示准备转换
int  : IN STD_LOGIC;         --数据输出信号
st  : IN STD_LOGIC;        --转换开始信号
CS   : OUT STD_LOGIC;           --数据输出3态控制信号
RD  : OUT STD_LOGIC;         --信号通道控制信号
Q  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8位数据输出
END module;
ARCHITECTURE behav OF module IS
TYPE states IS (st0, st1, st2, st3,st4) ; --定义各状态子类型
  SIGNAL current_state, next_state: states :=st0 ;
  SIGNAL REGL 	    : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL LOCK	    : STD_LOGIC; -- 转换后数据输出锁存时钟信号
 BEGIN
Q <= REGL; 
REG: PROCESS (CLK,st)  
    BEGIN
     IF (CLK'EVENT AND CLK='1') THEN current_state<=next_state; END IF;
   END PROCESS REG ;-- 由信号current_state将当前状态值带出此进程:REG
COM: PROCESS(current_state,rdy,int)  
   BEGIN  -----规定各状态转换方式
   CASE current_state IS           
   	WHEN st0=>cs<='1';rd<='1';
       	next_state <= st1; --0809初始化
	WHEN st1=>cs<='0';rd<='1';
	if(rdy='0' and int='1' ) then next_state <=st2;
	else next_state<=st1; end if;
    WHEN st2=>cs<='0';rd<='0';
    if (rdy='0' and int='1') THEN  next_state <= st3; --EOC=1表明转换结束
	else next_state<=st2; end if;                  --转换未结束，继续等待    
WHEN st3=>cs<='0';rd<='0'; 
  IF (rdy='1' and int='0') THEN next_state <= st4; --EOC=1表明转换结束
	 	ELSE next_state <= st3;  END IF ;    --转换未结束，继续等待  
WHEN st4=>cs<='0';rd<='0';
IF (rdy='1' and int='1') THEN next_state <= st0; --EOC=1表明转换结束
	 	ELSE next_state <= st4;  END IF ;    --转换未结束，继续等待  
WHEN OTHERS => next_state <= st0;
   END CASE ;
 END PROCESS COM ;  
  LATCH1: PROCESS (int) --此进程中，在LOCK的上升沿，将转换好的数据锁入
         BEGIN
IF ( int'EVENT AND INT='1')  THEN   REGL <= D ; END IF;
       END PROCESS LATCH1 ; 
  END behav;