2410init.s

ARM9-2410的LED灯点亮码源

	include ..\arm\2410addr.inc
	include ..\arm\2410option.inc
	include ..\arm\2410memcfg.inc
BIT_SELFREFRESH EQU (1:SHL:22)
USERMODE  EQU 0x10
FIQMODE   EQU 0x11
IRQMODE   EQU 0x12
SVCMODE   EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK  EQU 0x1f
NOINT	  EQU 0xc0

SVCStack   EQU (_STACK_BASEADDRESS-0x3800);0x30ff4800
UserStack  EQU (_STACK_BASEADDRESS-0x2800);0x30ff5800
UndefStack EQU (_STACK_BASEADDRESS-0x2400);0x30ff5c00
AbortStack EQU (_STACK_BASEADDRESS-0x2000);0x30ff6000
IRQStack   EQU (_STACK_BASEADDRESS-0x1000);0x30ff7000
FIQStack   EQU (_STACK_BASEADDRESS-0x0)	 ;0x30ff8000

			
	macro 
$label HANDLER  $HandleLabel
	
$label
	sub sp,sp,#4			;;@decrement sp(to store jump address)
	stmfd sp!,{r0}		;;@PUSH the work register to stack(lr does not push because it return to original address)
	ldr     r0,=$HandleLabel	;;@load the address of HandleXXX to r0
	ldr     r0,[r0]		;;@load the contents(service routine start address) of HandleXXX
	str     r0,[sp,#4]		;;@store the contents(ISR) of HandleXXX to stack
	ldmfd   sp!,{r0,pc}		;;@POP the work register and pc(jump to ISR)
	mend
	
    IMPORT	|Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
    IMPORT	|Image$$RW$$Base|   ; Base of RAM to initialise
    IMPORT	|Image$$ZI$$Base|   ; Base and limit of area
    IMPORT	|Image$$ZI$$Limit|  ; to zero initialise
	IMPORT Main			;@ The main entry of mon program

	CODE32
	
	AREA  INIT,CODE,READONLY
		ENTRY
	
	b	ResetHandler  
	b	HandlerUndef	
	b	HandlerSWI	    
	b	HandlerPabort	
	b	HandlerDabort
	b	.		        
	b	HandlerIRQ	   
	b	HandlerFIQ	    
	;***IMPORTANT NOTE***
	;If the H/W vectored interrutp mode is enabled, The above two instructions should
	;be changed like below, to work-around with H/W bug of S3C44B0X interrupt controller. 
	; b HandlerIRQ  ->  subs pc,lr,#4
	; b HandlerIRQ  ->  subs pc,lr,#4

	LTORG   
HandlerFIQ      HANDLER HandleFIQ
HandlerIRQ      HANDLER HandleIRQ
HandlerUndef    HANDLER HandleUndef
HandlerSWI      HANDLER HandleSWI
HandlerDabort   HANDLER HandleDabort
HandlerPabort   HANDLER HandlePabort

;ISR Handle
IsrIRQ
	sub	sp,sp,#4        ;@reserved for PC    
	stmfd	sp!,{r8-r9}   
	
	ldr	r9,=INTOFFSET
	ldr	r9,[r9]            ;@ Load the INTOFFSET register value to r9
	ldr	r8,=HandleEINT0    ;@ Load the ISR vector base address to r8
	add	r8,r8,r9,lsl #2    ;@ get the ISR vector r8 = r8 + r9 * 4
	ldr	r8,[r8]            ;@ Load the ISR address
	str	r8,[sp,#8]         ;@ store to sp, new PC
	ldmfd	sp!,{r8-r9,pc}     ;@ jump to new PC, that is to ISR
;entry
ResetHandler
	ldr	r0,=WTCON       ;@watch dog disable 
	ldr	r1,=0x0         
	str	r1,[r0]

	ldr	r0,=INTMSK
	ldr	r1,=0xffffffff  ;@all interrupt disable
	str	r1,[r0]

	ldr	r0,=INTSUBMSK
	ldr	r1,=0x3ff		;@all sub interrupt disable
	str	r1,[r0]
	
	;@To reduce PLL lock time, adjust the LOCKTIME register.
	ldr	r0,=LOCKTIME
	ldr	r1,=0xffffff
	str	r1,[r0]
	
	IF :DEF:  PLL_ON_START
	;@Configure MPLL
	ldr r0,=MPLLCON          
    ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)
    str r1,[r0]
	ENDIF
	;@ Set memory control registers
	ldr	r0,=SMRDATA
	ldr	r1,=BWSCON	;@BWSCON Address
	add	r2, r0, #52	;@End address of SMRDATA
0  
	ldr	r3, [r0], #4    
	str	r3, [r1], #4    
	cmp	r2, r0		
	bne	%B0
	
	;@Initialize stacks	
 	bl	InitStacks
	
	;@ Setup IRQ handler
	ldr	r0,=HandleIRQ       ;@This routine is needed
	ldr	r1,=IsrIRQ          ;@if there isn't 'subs pc,lr,#4 at 0x18, 0x1c
	str	r1,[r0]

	;@ Copy and paste RW data/zero initialized data
	ldr	r0, =|Image$$RO$$Limit| ;@ Get pointer to ROM data
	ldr	r1, =|Image$$RW$$Base|  ;@ and RAM copy
	ldr	r3, =|Image$$ZI$$Base|  
	
	;@ Zero init base => top of initialised data
	cmp	r0, r1    ;@ Check that they are different 
	beq	%F2
1       
	cmp	r1, r3      	  ;@ Copy init data
	ldrcc	r2, [r0], #4    ;@--> LDRCC r2, [r0] + ADD r0, r0, #4         
	strcc	r2, [r1], #4    ;@--> STRCC r2, [r1] + ADD r1, r1, #4
	bcc	%B1
2       
	ldr	r1,=|Image$$ZI$$Limit| ;@ Top of zero init segment
	mov	r2, #0
3       
	cmp	r3, r1     	;@ Zero init
	strcc	r2, [r3], #4
	bcc	%B3		

   	bl	Main        
   	b	.  
;@===================================================================================
;@ Initializing stacks
;@     Do not use DRAM,such as stmfd,ldmfd......
;@     SVCstack is initialized before
;@     Under toolkit ver 2.5, msr cpsr,r1 can be used instead of msr cpsr_cxsf,r1
;@===================================================================================	
InitStacks
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#(UNDEFMODE|NOINT)
	msr	cpsr_cxsf,r1			;@UndefMode		
	ldr	sp,=UndefStack
	
	orr	r1,r0,#(ABORTMODE|NOINT)
	msr	cpsr_cxsf,r1			;@AbortMode		
	ldr	sp,=AbortStack

	orr	r1,r0,#(IRQMODE|NOINT)
	msr	cpsr_cxsf,r1			;@IRQMode		
	ldr	sp,=IRQStack
    
	orr	r1,r0,#(FIQMODE|NOINT)
	msr	cpsr_cxsf,r1			;@FIQMode		
	ldr	sp,=FIQStack

	bic	r0,r0,#(MODEMASK|NOINT)
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1			;@SVCMode	
	ldr	sp,=SVCStack
	
	;USER mode is not initialized.
    	mov	    pc,lr ;The LR register may be not valid for the mode changes

;@===================================================================
;@ Memory configuration:
;@     Memory configuration should be optimized for best performance 
;@     The following parameter is not optimized.                     
;@     Memory access cycle parameter strategy
;@     1. The memory settings is  safe parameters even at HCLK=75Mhz.
;@     2. SDRAM refresh period is for HCLK=75Mhz. 
;@===================================================================
	LTORG
	
	AREA SMRDATA,DATA,READWRITE
	
    DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))  
    DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))  
    DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   
    DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   
    DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   
    DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   
    DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    
    DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    
    DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+REFCNT)       
    DCD 0xb2           
    DCD 0x30            
    DCD 0x30   
;@=========================================
;@ Exception vector table
;@=========================================
HandleReset 	 EQU _ISR_STARTADDRESS        
HandleUndef 	 EQU _ISR_STARTADDRESS + 0x4  
HandleSWI 	     EQU _ISR_STARTADDRESS + 0x8 
HandlePabort 	 EQU _ISR_STARTADDRESS + 0xc 
HandleDabort 	 EQU _ISR_STARTADDRESS + 0x10
HandleReserved 	 EQU _ISR_STARTADDRESS + 0x14
HandleIRQ 	     EQU _ISR_STARTADDRESS + 0x18 
HandleFIQ 	     EQU _ISR_STARTADDRESS + 0x1c

;@=========================================
;@ Interrupt vector table
;@=========================================
HandleEINT0 	 EQU _ISR_STARTADDRESS + 0x20 
HandleEINT1 	 EQU _ISR_STARTADDRESS + 0x24 
HandleEINT2 	 EQU _ISR_STARTADDRESS + 0x28 
HandleEINT3 	 EQU _ISR_STARTADDRESS + 0x2c 
HandleEINT4_7  	 EQU _ISR_STARTADDRESS + 0x30 
HandleEINT8_23 	 EQU _ISR_STARTADDRESS + 0x34 
HandleRSV6     	 EQU _ISR_STARTADDRESS + 0x38 
HandleBATFLT 	 EQU _ISR_STARTADDRESS + 0x3c 
HandleTICK 	     EQU _ISR_STARTADDRESS + 0x40 
HandleWDT 	     EQU _ISR_STARTADDRESS + 0x44 
HandleTIMER0 	 EQU _ISR_STARTADDRESS + 0x48 
HandleTIMER1 	 EQU _ISR_STARTADDRESS + 0x4c 
HandleTIMER2 	 EQU _ISR_STARTADDRESS + 0x50 
HandleTIMER3 	 EQU _ISR_STARTADDRESS + 0x54 
HandleTIMER4 	 EQU _ISR_STARTADDRESS + 0x58 
HandleUART2 	 EQU _ISR_STARTADDRESS + 0x5c 
HandleLCD 	     EQU _ISR_STARTADDRESS + 0x60 
HandleDMA0 	     EQU _ISR_STARTADDRESS + 0x64 
HandleDMA1 	     EQU _ISR_STARTADDRESS + 0x68 
HandleDMA2 	     EQU _ISR_STARTADDRESS + 0x6c 
HandleDMA3 	     EQU _ISR_STARTADDRESS + 0x70 
HandleMMC 	     EQU _ISR_STARTADDRESS + 0x74 
HandleSPI0 	     EQU _ISR_STARTADDRESS + 0x78 
HandleUART1 	 EQU _ISR_STARTADDRESS + 0x7c 
HandleRSV24 	 EQU _ISR_STARTADDRESS + 0x80 
HandleUSBD     	 EQU _ISR_STARTADDRESS + 0x84 
HandleUSBH     	 EQU _ISR_STARTADDRESS + 0x88 
HandleIIC     	 EQU _ISR_STARTADDRESS + 0x8c  
HandleUART0      EQU _ISR_STARTADDRESS + 0x90 
HandleSPI1 	     EQU  _ISR_STARTADDRESS + 0x94 
HandleRTC 	     EQU _ISR_STARTADDRESS + 0x98 
HandleADC 	     EQU _ISR_STARTADDRESS + 0x9c 

	        

	END