i2220hw.h

Driver for IPN2220 for Linux

/*
** $Id: i2220hw.h 1.37 2004/05/10 22:24:29 chyeh Exp $
*/

/******************************************************************************
Copyright (c) 2002-2003 Integrated Programmable Communications, Inc.

All rights reserved. Copying, compilation, modification, distribution
or any other use whatsoever of this material is strictly prohibited
except in accordance with a Software License Agreement with
Integrated Programmable Communications, Inc.
******************************************************************************/

#ifndef _I2220_HARDWARE_H
#define _I2220_HARDWARE_H

/************************************************************************
*                     C O M P I L E R   F L A G S
*************************************************************************
*/

/************************************************************************
*                E X T E R N A L   R E F E R E N C E S
*************************************************************************
*/

/************************************************************************
*                          C O N S T A N T S
*************************************************************************
*/
/* The number of transmit queues */
#define NUM_TDMA_CHANNELS               NUM_TX_QUEUES

#define MAX_MULTICAST_ADDRESSES         32
#define MAX_HW_MULTICAST_REGS           6

/* Host Maintained State Info */
#define I2220HW_STATE_PREINIT           0
#define I2220HW_STATE_INIT              1
#define I2220HW_STATE_RUNNING           2
#define I2220HW_STATE_SCANNING          3

#define TX_TFCB_SUCCESS_MORE_BUFF       0
#define TX_TFCB_SUCCESS_NO_BUFF         1
#define TX_TFCB_FAILURE                 2

/* Return code of env_PHY_SAP_RX() */
#define RX_DRV_HANDLED_PACKET           0
#define RX_INDICATE_PACKET_UPWARD       1

/* Basic interval of checking adjacent channel noise, in unit of Kus */
#define CHECK_ADJ_CHNL_INTERVAL         1000

/* Define how many Beacon not sent out to reset MAC */
#define BCN_TX_LOSS_LIMIT               4

#if SUPPORT_TKIP
#define TKIP_HW_MIC_TBB_NUM_PER_TFCB    3
#endif

/************************************************************************
*                         D A T A   T Y P E S
*************************************************************************
*/

/* Transmit Buffer Block (TBB) */
__KAL_PACK_BEGIN__
typedef struct _hw_tbb_t {
    /* transmit buffer descriptor (TBD) (0x00 -- 0x07) */
    UCHAR       tbbFlags;               /* 0x00: TBB flags - EOL bit */
    UCHAR       tbdChecksum;            /* 0x01: TBD checksum */
    USHORT      txDataBufferLen;        /* 0x02-0x03: transmit data buffer length */
    ULONG       nextTbbPointer;         /* 0x04-0x07: next TBB pointer */
    ULONG       txDataBufferPointer;    /* 0x08-0x0b: transmit data buffer pointer */
    /* reserved space for LLC or security padding */
    UCHAR       revBuf[TBB_REVBUFFER_SIZE];
} __KAL_ATTRIB_PACKED__ hw_tbb_t;
__KAL_PACK_END__

typedef struct _tbb_t {
    hw_tbb_t            hw;
    kal_dma_addr_t      dmaAddr;
    struct {
                /* Link to the next SW TBB in the list */
                struct list_head        link;
    } sw;
    BOOLEAN             do_map_unmap;   /* TRUE: need to do pci_unmap_single() */
} tbb_t, *ptbb_t;

/* Transmit Frame Control Block (TFCB) */
__KAL_PACK_BEGIN__
typedef struct _hw_tfcb_t {
    /* transmit frame descriptor (TFD) (0x00 -- 0x0f) */
    UCHAR       tfdCtrlFlag;        /* 0x00: TFD control flag - EOL, NB, More, CFB, SEC, and Paired */
    UCHAR       tfdChecksum;        /* 0x01: TFD checksum */
    UCHAR       reserved1[2];       /* 0x02-0x03: reserved */
    ULONG       tbbPointer;         /* 0x04-0x07: TBB pointer */
    ULONG       secModeDestAddr;    /* 0x08-0x0b: SEC mode operation result dest addr or TQ0/1 tx enable mapping */
    ULONG       nextTfcbPointer;    /* 0x0c-0x0f: Next TFCB pointer */
    /* security control information (0x10 -- 0x2b) */
    UCHAR       sciCtrlFlag;        /* 0x10: SCI control flag */
    UCHAR       secOpMode;          /* 0x11: security operation mode */
    UCHAR       dmaFifoHeaderLen;   /* 0x12: DMA FIFO header length */
    UCHAR       reserved2;          /* 0x13: reserved */
    //ULONG       sciIv;              /* 0x14-0x17: SCI IV */
    union{
        ULONG       sciIv;          /* 0x14-0x17: SCI IV */
        struct {
            UCHAR   initialVector[3];
            UCHAR   keyId;
        } __KAL_ATTRIB_PACKED__ s;
    } __KAL_ATTRIB_PACKED__ u_sciiv;
    ULONG       sciExtendedIv;      /* 0x18-0x1b: SCI extended IV */
    UCHAR       encryptionKey[16];  /* 0x1c-0x2b: encryption key */
    /* transmit control information (0x2c -- 0x43) */
    UCHAR       tciCtrlFlag;        /* 0x2c: TCI control flag */
    UCHAR       rtsRetryLimit;      /* 0x2d: RTS retry limit */
    UCHAR       rtsCtsRate;         /* 0x2e: RTS/CTS rate */
    UCHAR       tidMacHdrCtrlFlag;  /* 0x2f: TID & MAC header control flag */
    USHORT      rtsCtsDuration;     /* 0x30-0x31: RTS/CTS duration field */
    USHORT      cfPollTxopLimit;    /* 0x32-0x33: CFPollTXOPLimit */
    USHORT      packetTxTime1;      /* 0x34-0x35: packet tx time 1 */
    USHORT      packetTxTime2;      /* 0x36-0x37: packet tx time 2 */
    USHORT      minFrameExchangeTime1;  /* 0x38-0x39: min frame exchange time 1 */
    USHORT      minFrameExchangeTime2;  /* 0x3a-0x3b: min frame exchange time 2 */
    USHORT      multirateSwCtrl;    /* 0x3c-0x3d: multirate switching control */
    USHORT      txRates;            /* 0x3e-0x3f: transmission rates */
    ULONG       tQ0IdxBitMap;       /* 0x40-0x43: TQ0 Index Bit map */
    UCHAR       txPower;            /* 0x44: Tramsmission power*/
    UCHAR       reserved3[3];       /* 0x45-0x47: reserved */
    USHORT      mpduLen;            /* 0x48-0x49: MPDU length */
    USHORT      totalTxDataLen;     /* 0x4a-0x4b: total tx data length */
    /* MAC header information (0x4c -- 0x77) */
    UCHAR       macHeaderLen;       /* 0x4c: MAC header length */
    UCHAR       reserved4;          /* 0x4d: reserved */
    USHORT      durationId2;        /* 0x4e-0x4f: duration/ID 2 */
    USHORT      frameCtrl;          /* 0x50-0x51: frame control */
    USHORT      durationId1;        /* 0x52-0x53: duration/ID 1 */
    UCHAR       macHeader[28];      /* 0x54-0x6f: MAC header field */
    ULONG       iv;                 /* 0x70-0x73: IV */
    ULONG       extendedIv;         /* 0x74-0x77: extended IV */
    /* transmit status information (0x78 -- 0x87) */
    ULONG       txTimestamp[2];     /* 0x78-0x7f: transmit timestamp */
    USHORT      txedPower;          /* 0x80-0x81: measured transmitted power */
    USHORT      reserved5;
    USHORT      txStatus;           /* 0x84-0x85: transmit status */
    UCHAR       rtsRetryCount;      /* 0x86: RTS retry count */
    UCHAR       mpduRetryCount;     /* 0x87: MPDU retry count */
} __KAL_ATTRIB_PACKED__ hw_tfcb_t;
__KAL_PACK_END__

typedef hw_tfcb_t *PTFCB_STRUC;

typedef struct _tfcb_t  {
    hw_tfcb_t           hw;
    kal_dma_addr_t      dmaAddr;
    struct _tfcb_t      *nextTfcb;   /* tracking for tx and sec queues */
    UINT8               tkipMic[48];
    struct {
        /* Link to the next SW_TFCB in the list */
        struct list_head    link;

        /* Link to the first TBB in the list */
        struct list_head    tbb_list;

        /* the associated frame struct pointer, which hold the memory of
         * the frame body, should be released altogether after TDMA done.
         */
        FragSdu_t           *fsdu;
        int                 frag_nr;

        /* The transmit start time that is used to check for hang. */
        //UINT32              transmitStartTime;
    } sw;
} tfcb_t, *ptfcb_t;

/* Receive Frame Block (RFB) (Receive Buffer included) */
__KAL_PACK_BEGIN__
typedef struct _hw_rfb_t {
    /* receive frame descriptor (RFB) (0x00 -- 0x0b) */
    UCHAR       rfbFlags;               /* 0x00: RFB flags - EOL bit */
    UCHAR       reserved1[2];           /* 0x01-0x02: reserved */
    UCHAR       rfdChecksum;            /* 0x03: RFD checksum */
    ULONG       rxBufferPointer;        /* 0x04-0x07: receive buffer pointer */
    ULONG       nextRfbPointer;         /* 0x08-0x0b: next RFB pointer */
    /* receive status information (0x0c -- 0x2b) */
    ULONG       fcs;                    /* 0x0c-0x0f: FCS */
    ULONG       rxTimestamp[2];         /* 0x10-0x17: receive timestamp */
    ULONG       rxStatus;               /* 0x18-0x1b: receive status */
    ULONG       rxByteCount;            /* 0x1c-0x1f: receive byte count */
    UCHAR       bbCr24;                 /* 0x20: baseband CR 24 */
    UCHAR       bbCr25;                 /* 0x21: baseband CR 25 */
    UCHAR       bbCr26;                 /* 0x22: baseband CR 26 */
    UCHAR       bbCr27;                 /* 0x23: baseband CR 27 */
    UCHAR       bbCr28;                 /* 0x24: baseband CR 28 */
    UCHAR       bbCr29;                 /* 0x25: baseband CR 29 */
    UCHAR       bbCr30;                 /* 0x26: baseband CR 30 */
    UCHAR       bbCr31;                 /* 0x27: baseband CR 31 */
    UCHAR       bbCr32;                 /* 0x28: baseband CR 32 */
    UCHAR       bbCr33;                 /* 0x29: baseband CR 33 */
    UCHAR       bbCr34;                 /* 0x2a: baseband CR 34 */
    UCHAR       bbCr35;                 /* 0x2b: baseband CR 35 */
    UCHAR       bbCrA;                  /* 0x2c: baseband CR A */
    UCHAR       bbCrB;                  /* 0x2d: baseband CR B */
    UCHAR       bbCrC;                  /* 0x2e: baseband CR C */
    UCHAR       bbCrD;                  /* 0x2f: baseband CR D */
    /* security receive status */
    ULONG       secStatus;              /* 0x30-0x33: receive status for security */
    ULONG       iv;                     /* 0x34-0x37: IV */
    ULONG       extendedIv;             /* 0x38-0x3b: extended IV */
} __KAL_ATTRIB_PACKED__ hw_rfb_t;
__KAL_PACK_END__

typedef struct _rfb_t {
    hw_rfb_t            hw;
    kal_dma_addr_t      dmaAddr;
    struct {
        struct list_head    link;
        kal_skb_t           *rfb_skb;   /* the associated socket buffer */
        UINT32              secMode;
        UINT32              keyId;
    } sw;
    //UINT32                  secStatus;  /* receive security status (quick retrieval) */
} rfb_t, *prfb_t;

/* TDMA_PARAMETERS - The TDMA parameters structure definition. */
typedef struct _tdma_parameters {
        TX_QUEUE_NUM    tdmaChannel;    /* correspoding to TXQ_xxx */
        tfcb_t          *head_p;        /* TDMA transfering in progress */
        tfcb_t          *tail_p;        /* Should be an EOL TFCB */
        int             count;          /* number of TFCB including EOL TFCB */
        chain_list_t    waitQ;          /* FragSdu_t wait for tx out in this channel */
} tdma_parameters_t;


/************************************************************************
*                        P U B L I C   D A T A
*************************************************************************
*/

/************************************************************************
*                             M A C R O S
*************************************************************************
*/

#define tfcb_for_each(head,tfcb_p) \
        for ( tfcb_p = head; \
              (tfcb_p->hw.tfdCtrlFlag & TFCB_FLAG_EOL) == 0; \
              tfcb_p = tfcb_p->nextTfcb \
            )

#define tx_check_TDMA(chain_p,nTFCB,nTBB) ( \
        chain_num_elem(chain_p) >= (nTFCB) && \
        chain_num_elem(&priv_p->tbb_chain) >= (nTBB) )

// Additional piggybacked information on sk_buff
// 1. The TimeStamp information, for performance measurement
#define skb_set_Flag(skb,f)             ( *(UINT32*)(&(skb)->cb[0]) |= f )
#define skb_get_Flag(skb)               ( *(UINT32*)(&(skb)->cb[0]) )
#define skb_clear_Flag(skb)             ( *(UINT32*)(&(skb)->cb[0]) = 0 )
#define skb_set_TimeStamp(skb,t)        ( *(UINT32*)(&(skb)->cb[4]) = t )
#define skb_get_TimeStamp(skb)          ( *(UINT32*)(&(skb)->cb[4]) )

// For skb_set_Flag/get macros
#define SKB_TSTAMP_IN_USE       BIT(0)

#ifdef IPN_NEW_KAL
/* Endian conversion of MAC Hardware intergers to/from HOST */
#if __CPU_ENDIAN__ != __LITTLE_ENDIAN__
#define chip2host_16(n)         __swap16(n)
#define chip2host_32(n)         __swap32(n)
#define host2chip_16(n)         __swap16(n)
#define host2chip_32(n)         __swap32(n)
#else
#define chip2host_16(n)         (n)
#define chip2host_32(n)         (n)
#define host2chip_16(n)         (n)
#define host2chip_32(n)         (n)
#endif
#endif
/************************************************************************
*                 F U N C T I O N   D E C L A R A T I O N S
*************************************************************************
*/

/************************************************************************
*           I N L I N E   F U N C T I O N   D E F I N I T I O N S
*************************************************************************
*/

#endif /* _I2220_HARDWARE_H */