📄 defbf532.h
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// SIC_IAR2 Masks
#define P16_IVG(x) ((x)-7) // Peripheral #16 assigned IVG #x
#define P17_IVG(x) ((x)-7) << 0x4 // Peripheral #17 assigned IVG #x
#define P18_IVG(x) ((x)-7) << 0x8 // Peripheral #18 assigned IVG #x
#define P19_IVG(x) ((x)-7) << 0xC // Peripheral #19 assigned IVG #x
#define P20_IVG(x) ((x)-7) << 0x10 // Peripheral #20 assigned IVG #x
#define P21_IVG(x) ((x)-7) << 0x14 // Peripheral #21 assigned IVG #x
#define P22_IVG(x) ((x)-7) << 0x18 // Peripheral #22 assigned IVG #x
#define P23_IVG(x) ((x)-7) << 0x1C // Peripheral #23 assigned IVG #x
// SIC_IMASK Masks
#define SIC_UNMASK_ALL 0x00000000 // Unmask all peripheral interrupts
#define SIC_MASK_ALL 0xFFFFFFFF // Mask all peripheral interrupts
#define SIC_MASK(x) (1 << (x)) // Mask Peripheral #x interrupt
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) // Unmask Peripheral #x interrupt
// SIC_IWR Masks
#define IWR_DISABLE_ALL 0x00000000 // Wakeup Disable all peripherals
#define IWR_ENABLE_ALL 0xFFFFFFFF // Wakeup Enable all peripherals
#define IWR_ENABLE(x) (1 << (x)) // Wakeup Enable Peripheral #x
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) // Wakeup Disable Peripheral #x
// ********* WATCHDOG TIMER MASKS ********************8
// Watchdog Timer WDOG_CTL Register
#define ICTL(x) ((x<<1) & 0x0006)
#define ENABLE_RESET 0x00000000 // Set Watchdog Timer to generate reset
#define ENABLE_NMI 0x00000002 // Set Watchdog Timer to generate non-maskable interrupt
#define ENABLE_GPI 0x00000004 // Set Watchdog Timer to generate general-purpose interrupt
#define DISABLE_EVT 0x00000006 // Disable Watchdog Timer interrupts
#define TMR_EN 0x0000
#define TMR_DIS 0x0AD0
#define TRO 0x8000
#define ICTL_P0 0x01
#define ICTL_P1 0x02
#define TRO_P 0x0F
// RTC_STAT and RTC_ALARM register
#define RTSEC 0x0000003F // Real-Time Clock Seconds
#define RTMIN 0x00000FC0 // Real-Time Clock Minutes
#define RTHR 0x0001F000 // Real-Time Clock Hours
#define RTDAY 0xFFFE0000 // Real-Time Clock Days
// RTC_ICTL register
#define SWIE 0x0001 // Stopwatch Interrupt Enable
#define AIE 0x0002 // Alarm Interrupt Enable
#define SIE 0x0004 // Seconds (1 Hz) Interrupt Enable
#define MIE 0x0008 // Minutes Interrupt Enable
#define HIE 0x0010 // Hours Interrupt Enable
#define DIE 0x0020 // 24 Hours (Days) Interrupt Enable
#define DAIE 0x0040 // Day Alarm (Day, Hour, Minute, Second) Interrupt Enable
#define WCIE 0x8000 // Write Complete Interrupt Enable
// RTC_ISTAT register
#define SWEF 0x0001 // Stopwatch Event Flag
#define AEF 0x0002 // Alarm Event Flag
#define SEF 0x0004 // Seconds (1 Hz) Event Flag
#define MEF 0x0008 // Minutes Event Flag
#define HEF 0x0010 // Hours Event Flag
#define DEF 0x0020 // 24 Hours (Days) Event Flag
#define DAEF 0x0040 // Day Alarm (Day, Hour, Minute, Second) Event Flag
#define WPS 0x4000 // Write Pending Status (RO)
#define WCOM 0x8000 // Write Complete
//// RTC_FAST Mask (RTC_PREN Mask)
#define ENABLE_PRESCALE 0x00000001 // Enable prescaler so RTC runs at 1 Hz
#define PREN 0x00000001
// ** Must be set after power-up for proper operation of RTC
// ***************************** UART CONTROLLER MASKS **********************
// UART_LCR Register
#define DLAB 0x80
#define SB 0x40
#define STP 0x20
#define EPS 0x10
#define PEN 0x08
#define STB 0x04
#define WLS(x) ((x-5) & 0x03)
#define DLAB_P 0x07
#define SB_P 0x06
#define STP_P 0x05
#define EPS_P 0x04
#define PEN_P 0x03
#define STB_P 0x02
#define WLS_P1 0x01
#define WLS_P0 0x00
// UART_MCR Register
#define LOOP 0x10
#define LOOP_P 0x04
// UART_LSR Register
#define TEMT 0x40
#define THRE 0x20
#define BI 0x10
#define FE 0x08
#define PE 0x04
#define OE 0x02
#define DR 0x01
#define TEMP_P 0x06
#define THRE_P 0x05
#define BI_P 0x04
#define FE_P 0x03
#define PE_P 0x02
#define OE_P 0x01
#define DR_P 0x00
// UART_IER Register
#define ELSI 0x04
#define ETBEI 0x02
#define ERBFI 0x01
#define ELSI_P 0x02
#define ETBEI_P 0x01
#define ERBFI_P 0x00
// UART_IIR Register
#define STATUS(x) ((x << 1) & 0x06)
#define NINT 0x01
#define STATUS_P1 0x02
#define STATUS_P0 0x01
#define NINT_P 0x00
// UART_GCTL Register
#define FFE 0x20
#define FPE 0x10
#define RPOLC 0x08
#define TPOLC 0x04
#define IREN 0x02
#define UCEN 0x01
#define FFE_P 0x05
#define FPE_P 0x04
#define RPOLC_P 0x03
#define TPOLC_P 0x02
#define IREN_P 0x01
#define UCEN_P 0x00
// ********** SERIAL PORT MASKS **********************
// SPORTx_TCR1 Masks
#define TSPEN 0x0001 // TX enable
#define ITCLK 0x0002 // Internal TX Clock Select
#define TDTYPE 0x000C // TX Data Formatting Select
#define TLSBIT 0x0010 // TX Bit Order
#define ITFS 0x0200 // Internal TX Frame Sync Select
#define TFSR 0x0400 // TX Frame Sync Required Select
#define DITFS 0x0800 // Data Independent TX Frame Sync Select
#define LTFS 0x1000 // Low TX Frame Sync Select
#define LATFS 0x2000 // Late TX Frame Sync Select
#define TCKFE 0x4000 // TX Clock Falling Edge Select
// SPORTx_TCR2 Masks
#define SLEN 0x001F //TX Word Length
#define TXSE 0x0100 //TX Secondary Enable
#define TSFSE 0x0200 //TX Stereo Frame Sync Enable
#define TRFST 0x0400 //TX Right-First Data Order
// SPORTx_RCR1 Masks
#define RSPEN 0x0001 // RX enable
#define IRCLK 0x0002 // Internal RX Clock Select
#define RDTYPE 0x000C // RX Data Formatting Select
#define RULAW 0x0008 // u-Law enable
#define RALAW 0x000C // A-Law enable
#define RLSBIT 0x0010 // RX Bit Order
#define IRFS 0x0200 // Internal RX Frame Sync Select
#define RFSR 0x0400 // RX Frame Sync Required Select
#define LRFS 0x1000 // Low RX Frame Sync Select
#define LARFS 0x2000 // Late RX Frame Sync Select
#define RCKFE 0x4000 // RX Clock Falling Edge Select
// SPORTx_RCR2 Masks
#define SLEN 0x001F //RX Word Length
#define RXSE 0x0100 //RX Secondary Enable
#define RSFSE 0x0200 //RX Stereo Frame Sync Enable
#define RRFST 0x0400 //Right-First Data Order
//SPORTx_STAT Masks
#define RXNE 0x0001 //RX FIFO Not Empty Status
#define RUVF 0x0002 //RX Underflow Status
#define ROVF 0x0004 //RX Overflow Status
#define TXF 0x0008 //TX FIFO Full Status
#define TUVF 0x0010 //TX Underflow Status
#define TOVF 0x0020 //TX Overflow Status
#define TXHRE 0x0040 //TX Hold Register Empty
//SPORTx_MCMC1 Masks
#define WSIZE 0x0000F000 //Multichannel Window Size Field
#define WOFF 0x000003FF //Multichannel Window Offset Field
//SPORTx_MCMC2 Masks
#define MCCRM 0x00000003 //Multichannel Clock Recovery Mode
#define MCDTXPE 0x00000004 //Multichannel DMA Transmit Packing
#define MCDRXPE 0x00000008 //Multichannel DMA Receive Packing
#define MCMEN 0x00000010 //Multichannel Frame Mode Enable
#define FSDR 0x00000080 //Multichannel Frame Sync to Data Relationship
#define MFD 0x0000F000 //Multichannel Frame Delay
// ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************
//// PPI_CONTROL Masks
#define PORT_EN 0x00000001 // PPI Port Enable
#define PORT_DIR 0x00000002 // PPI Port Direction
#define XFR_TYPE 0x0000000C // PPI Transfer Type
#define PORT_CFG 0x00000030 // PPI Port Configuration
#define FLD_SEL 0x00000040 // PPI Active Field Select
#define PACK_EN 0x00000080 // PPI Packing Mode
#define DMA32 0x00000100 // PPI 32-bit DMA Enable
#define SKIP_EN 0x00000200 // PPI Skip Element Enable
#define SKIP_EO 0x00000400 // PPI Skip Even/Odd Elements
#define DLENGTH 0x00003800 // PPI Data Length
#define DLEN_8 0x0 // PPI Data Length mask for DLEN=8
#define DLEN(x) (((x-9) & 0x07) << 11) // PPI Data Length (only works for x=10-->x=16)
#define POL 0x0000C000 // PPI Signal Polarities
//// PPI_STATUS Masks
#define FLD 0x00000400 // Field Indicator
#define FT_ERR 0x00000800 // Frame Track Error
#define OVR 0x00001000 // FIFO Overflow Error
#define UNDR 0x00002000 // FIFO Underrun Error
#define ERR_DET 0x00004000 // Error Detected Indicator
#define ERR_NCOR 0x00008000 // Error Not Corrected Indicator
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