📄 defbf532.h
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#define EBIU_SDBCTL 0xFFC00A14 // SDRAM Bank Control Register
#define EBIU_SDRRC 0xFFC00A18 // SDRAM Refresh Rate Control Register
#define EBIU_SDSTAT 0xFFC00A1C // SDRAM Status Register
//// DMA Controller (0xFFC00C00 - 0xFFC00FFF)
#define DMA0_CONFIG 0xFFC00C08 // DMA Channel 0 Configuration Register
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 // DMA Channel 0 Next Descriptor Pointer Register
#define DMA0_START_ADDR 0xFFC00C04 // DMA Channel 0 Start Address Register
#define DMA0_X_COUNT 0xFFC00C10 // DMA Channel 0 X Count Register
#define DMA0_Y_COUNT 0xFFC00C18 // DMA Channel 0 Y Count Register
#define DMA0_X_MODIFY 0xFFC00C14 // DMA Channel 0 X Modify Register
#define DMA0_Y_MODIFY 0xFFC00C1C // DMA Channel 0 Y Modify Register
#define DMA0_CURR_DESC_PTR 0xFFC00C20 // DMA Channel 0 Current Descriptor Pointer Register
#define DMA0_CURR_ADDR 0xFFC00C24 // DMA Channel 0 Current Address Register
#define DMA0_CURR_X_COUNT 0xFFC00C30 // DMA Channel 0 Current X Count Register
#define DMA0_CURR_Y_COUNT 0xFFC00C38 // DMA Channel 0 Current Y Count Register
#define DMA0_IRQ_STATUS 0xFFC00C28 // DMA Channel 0 Interrupt/Status Register
#define DMA0_PERIPHERAL_MAP 0xFFC00C2C // DMA Channel 0 Peripheral Map Register
#define DMA1_CONFIG 0xFFC00C48 // DMA Channel 1 Configuration Register
#define DMA1_NEXT_DESC_PTR 0xFFC00C40 // DMA Channel 1 Next Descriptor Pointer Register
#define DMA1_START_ADDR 0xFFC00C44 // DMA Channel 1 Start Address Register
#define DMA1_X_COUNT 0xFFC00C50 // DMA Channel 1 X Count Register
#define DMA1_Y_COUNT 0xFFC00C58 // DMA Channel 1 Y Count Register
#define DMA1_X_MODIFY 0xFFC00C54 // DMA Channel 1 X Modify Register
#define DMA1_Y_MODIFY 0xFFC00C5C // DMA Channel 1 Y Modify Register
#define DMA1_CURR_DESC_PTR 0xFFC00C60 // DMA Channel 1 Current Descriptor Pointer Register
#define DMA1_CURR_ADDR 0xFFC00C64 // DMA Channel 1 Current Address Register
#define DMA1_CURR_X_COUNT 0xFFC00C70 // DMA Channel 1 Current X Count Register
#define DMA1_CURR_Y_COUNT 0xFFC00C78 // DMA Channel 1 Current Y Count Register
#define DMA1_IRQ_STATUS 0xFFC00C68 // DMA Channel 1 Interrupt/Status Register
#define DMA1_PERIPHERAL_MAP 0xFFC00C6C // DMA Channel 1 Peripheral Map Register
#define DMA2_CONFIG 0xFFC00C88 // DMA Channel 2 Configuration Register
#define DMA2_NEXT_DESC_PTR 0xFFC00C80 // DMA Channel 2 Next Descriptor Pointer Register
#define DMA2_START_ADDR 0xFFC00C84 // DMA Channel 2 Start Address Register
#define DMA2_X_COUNT 0xFFC00C90 // DMA Channel 2 X Count Register
#define DMA2_Y_COUNT 0xFFC00C98 // DMA Channel 2 Y Count Register
#define DMA2_X_MODIFY 0xFFC00C94 // DMA Channel 2 X Modify Register
#define DMA2_Y_MODIFY 0xFFC00C9C // DMA Channel 2 Y Modify Register
#define DMA2_CURR_DESC_PTR 0xFFC00CA0 // DMA Channel 2 Current Descriptor Pointer Register
#define DMA2_CURR_ADDR 0xFFC00CA4 // DMA Channel 2 Current Address Register
#define DMA2_CURR_X_COUNT 0xFFC00CB0 // DMA Channel 2 Current X Count Register
#define DMA2_CURR_Y_COUNT 0xFFC00CB8 // DMA Channel 2 Current Y Count Register
#define DMA2_IRQ_STATUS 0xFFC00CA8 // DMA Channel 2 Interrupt/Status Register
#define DMA2_PERIPHERAL_MAP 0xFFC00CAC // DMA Channel 2 Peripheral Map Register
#define DMA3_CONFIG 0xFFC00CC8 // DMA Channel 3 Configuration Register
#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 // DMA Channel 3 Next Descriptor Pointer Register
#define DMA3_START_ADDR 0xFFC00CC4 // DMA Channel 3 Start Address Register
#define DMA3_X_COUNT 0xFFC00CD0 // DMA Channel 3 X Count Register
#define DMA3_Y_COUNT 0xFFC00CD8 // DMA Channel 3 Y Count Register
#define DMA3_X_MODIFY 0xFFC00CD4 // DMA Channel 3 X Modify Register
#define DMA3_Y_MODIFY 0xFFC00CDC // DMA Channel 3 Y Modify Register
#define DMA3_CURR_DESC_PTR 0xFFC00CE0 // DMA Channel 3 Current Descriptor Pointer Register
#define DMA3_CURR_ADDR 0xFFC00CE4 // DMA Channel 3 Current Address Register
#define DMA3_CURR_X_COUNT 0xFFC00CF0 // DMA Channel 3 Current X Count Register
#define DMA3_CURR_Y_COUNT 0xFFC00CF8 // DMA Channel 3 Current Y Count Register
#define DMA3_IRQ_STATUS 0xFFC00CE8 // DMA Channel 3 Interrupt/Status Register
#define DMA3_PERIPHERAL_MAP 0xFFC00CEC // DMA Channel 3 Peripheral Map Register
#define DMA4_CONFIG 0xFFC00D08 // DMA Channel 4 Configuration Register
#define DMA4_NEXT_DESC_PTR 0xFFC00D00 // DMA Channel 4 Next Descriptor Pointer Register
#define DMA4_START_ADDR 0xFFC00D04 // DMA Channel 4 Start Address Register
#define DMA4_X_COUNT 0xFFC00D10 // DMA Channel 4 X Count Register
#define DMA4_Y_COUNT 0xFFC00D18 // DMA Channel 4 Y Count Register
#define DMA4_X_MODIFY 0xFFC00D14 // DMA Channel 4 X Modify Register
#define DMA4_Y_MODIFY 0xFFC00D1C // DMA Channel 4 Y Modify Register
#define DMA4_CURR_DESC_PTR 0xFFC00D20 // DMA Channel 4 Current Descriptor Pointer Register
#define DMA4_CURR_ADDR 0xFFC00D24 // DMA Channel 4 Current Address Register
#define DMA4_CURR_X_COUNT 0xFFC00D30 // DMA Channel 4 Current X Count Register
#define DMA4_CURR_Y_COUNT 0xFFC00D38 // DMA Channel 4 Current Y Count Register
#define DMA4_IRQ_STATUS 0xFFC00D28 // DMA Channel 4 Interrupt/Status Register
#define DMA4_PERIPHERAL_MAP 0xFFC00D2C // DMA Channel 4 Peripheral Map Register
#define DMA5_CONFIG 0xFFC00D48 // DMA Channel 5 Configuration Register
#define DMA5_NEXT_DESC_PTR 0xFFC00D40 // DMA Channel 5 Next Descriptor Pointer Register
#define DMA5_START_ADDR 0xFFC00D44 // DMA Channel 5 Start Address Register
#define DMA5_X_COUNT 0xFFC00D50 // DMA Channel 5 X Count Register
#define DMA5_Y_COUNT 0xFFC00D58 // DMA Channel 5 Y Count Register
#define DMA5_X_MODIFY 0xFFC00D54 // DMA Channel 5 X Modify Register
#define DMA5_Y_MODIFY 0xFFC00D5C // DMA Channel 5 Y Modify Register
#define DMA5_CURR_DESC_PTR 0xFFC00D60 // DMA Channel 5 Current Descriptor Pointer Register
#define DMA5_CURR_ADDR 0xFFC00D64 // DMA Channel 5 Current Address Register
#define DMA5_CURR_X_COUNT 0xFFC00D70 // DMA Channel 5 Current X Count Register
#define DMA5_CURR_Y_COUNT 0xFFC00D78 // DMA Channel 5 Current Y Count Register
#define DMA5_IRQ_STATUS 0xFFC00D68 // DMA Channel 5 Interrupt/Status Register
#define DMA5_PERIPHERAL_MAP 0xFFC00D6C // DMA Channel 5 Peripheral Map Register
#define DMA6_CONFIG 0xFFC00D88 // DMA Channel 6 Configuration Register
#define DMA6_NEXT_DESC_PTR 0xFFC00D80 // DMA Channel 6 Next Descriptor Pointer Register
#define DMA6_START_ADDR 0xFFC00D84 // DMA Channel 6 Start Address Register
#define DMA6_X_COUNT 0xFFC00D90 // DMA Channel 6 X Count Register
#define DMA6_Y_COUNT 0xFFC00D98 // DMA Channel 6 Y Count Register
#define DMA6_X_MODIFY 0xFFC00D94 // DMA Channel 6 X Modify Register
#define DMA6_Y_MODIFY 0xFFC00D9C // DMA Channel 6 Y Modify Register
#define DMA6_CURR_DESC_PTR 0xFFC00DA0 // DMA Channel 6 Current Descriptor Pointer Register
#define DMA6_CURR_ADDR 0xFFC00DA4 // DMA Channel 6 Current Address Register
#define DMA6_CURR_X_COUNT 0xFFC00DB0 // DMA Channel 6 Current X Count Register
#define DMA6_CURR_Y_COUNT 0xFFC00DB8 // DMA Channel 6 Current Y Count Register
#define DMA6_IRQ_STATUS 0xFFC00DA8 // DMA Channel 6 Interrupt/Status Register
#define DMA6_PERIPHERAL_MAP 0xFFC00DAC // DMA Channel 6 Peripheral Map Register
#define DMA7_CONFIG 0xFFC00DC8 // DMA Channel 7 Configuration Register
#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 // DMA Channel 7 Next Descriptor Pointer Register
#define DMA7_START_ADDR 0xFFC00DC4 // DMA Channel 7 Start Address Register
#define DMA7_X_COUNT 0xFFC00DD0 // DMA Channel 7 X Count Register
#define DMA7_Y_COUNT 0xFFC00DD8 // DMA Channel 7 Y Count Register
#define DMA7_X_MODIFY 0xFFC00DD4 // DMA Channel 7 X Modify Register
#define DMA7_Y_MODIFY 0xFFC00DDC // DMA Channel 7 Y Modify Register
#define DMA7_CURR_DESC_PTR 0xFFC00DE0 // DMA Channel 7 Current Descriptor Pointer Register
#define DMA7_CURR_ADDR 0xFFC00DE4 // DMA Channel 7 Current Address Register
#define DMA7_CURR_X_COUNT 0xFFC00DF0 // DMA Channel 7 Current X Count Register
#define DMA7_CURR_Y_COUNT 0xFFC00DF8 // DMA Channel 7 Current Y Count Register
#define DMA7_IRQ_STATUS 0xFFC00DE8 // DMA Channel 7 Interrupt/Status Register
#define DMA7_PERIPHERAL_MAP 0xFFC00DEC // DMA Channel 7 Peripheral Map Register
#define MDMA_D1_CONFIG 0xFFC00E88 // MemDMA Stream 1 Destination Configuration Register
#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 // MemDMA Stream 1 Destination Next Descriptor Pointer Register
#define MDMA_D1_START_ADDR 0xFFC00E84 // MemDMA Stream 1 Destination Start Address Register
#define MDMA_D1_X_COUNT 0xFFC00E90 // MemDMA Stream 1 Destination X Count Register
#define MDMA_D1_Y_COUNT 0xFFC00E98 // MemDMA Stream 1 Destination Y Count Register
#define MDMA_D1_X_MODIFY 0xFFC00E94 // MemDMA Stream 1 Destination X Modify Register
#define MDMA_D1_Y_MODIFY 0xFFC00E9C // MemDMA Stream 1 Destination Y Modify Register
#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 // MemDMA Stream 1 Destination Current Descriptor Pointer Register
#define MDMA_D1_CURR_ADDR 0xFFC00EA4 // MemDMA Stream 1 Destination Current Address Register
#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 // MemDMA Stream 1 Destination Current X Count Register
#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 // MemDMA Stream 1 Destination Current Y Count Register
#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 // MemDMA Stream 1 Destination Interrupt/Status Register
#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC // MemDMA Stream 1 Destination Peripheral Map Register
#define MDMA_S1_CONFIG 0xFFC00EC8 // MemDMA Stream 1 Source Configuration Register
#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 // MemDMA Stream 1 Source Next Descriptor Pointer Register
#define MDMA_S1_START_ADDR 0xFFC00EC4 // MemDMA Stream 1 Source Start Address Register
#define MDMA_S1_X_COUNT 0xFFC00ED0 // MemDMA Stream 1 Source X Count Register
#define MDMA_S1_Y_COUNT 0xFFC00ED8 // MemDMA Stream 1 Source Y Count Register
#define MDMA_S1_X_MODIFY 0xFFC00ED4 // MemDMA Stream 1 Source X Modify Register
#define MDMA_S1_Y_MODIFY 0xFFC00EDC // MemDMA Stream 1 Source Y Modify Register
#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 // MemDMA Stream 1 Source Current Descriptor Pointer Register
#define MDMA_S1_CURR_ADDR 0xFFC00EE4 // MemDMA Stream 1 Source Current Address Register
#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 // MemDMA Stream 1 Source Current X Count Register
#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 // MemDMA Stream 1 Source Current Y Count Register
#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 // MemDMA Stream 1 Source Interrupt/Status Register
#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC // MemDMA Stream 1 Source Peripheral Map Register
#define MDMA_D0_CONFIG 0xFFC00E08 // MemDMA Stream 0 Destination Configuration Register
#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 // MemDMA Stream 0 Destination Next Descriptor Pointer Register
#define MDMA_D0_START_ADDR 0xFFC00E04 // MemDMA Stream 0 Destination Start Address Register
#define MDMA_D0_X_COUNT 0xFFC00E10 // MemDMA Stream 0 Destination X Count Register
#define MDMA_D0_Y_COUNT 0xFFC00E18 // MemDMA Stream 0 Destination Y Count Register
#define MDMA_D0_X_MODIFY 0xFFC00E14 // MemDMA Stream 0 Destination X Modify Register
#define MDMA_D0_Y_MODIFY 0xFFC00E1C // MemDMA Stream 0 Destination Y Modify Register
#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 // MemDMA Stream 0 Destination Current Descriptor Pointer Register
#define MDMA_D0_CURR_ADDR 0xFFC00E24 // MemDMA Stream 0 Destination Current Address Register
#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 // MemDMA Stream 0 Destination Current X Count Register
#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 // MemDMA Stream 0 Destination Current Y Count Register
#define MDMA_D0_IRQ_STATUS 0xFFC00E28 // MemDMA Stream 0 Destination Interrupt/Status Register
#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C // MemDMA Stream 0 Destination Peripheral Map Register
#define MDMA_S0_CONFIG 0xFFC00E48 // MemDMA Stream 0 Source Configuration Register
#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 // MemDMA Stream 0 Source Next Descriptor Pointer Register
#define MDMA_S0_START_ADDR 0xFFC00E44 // MemDMA Stream 0 Source Start Address Register
#define MDMA_S0_X_COUNT 0xFFC00E50 // MemDMA Stream 0 Source X Count Register
#define MDMA_S0_Y_COUNT 0xFFC00E58 // MemDMA Stream 0 Source Y Count Register
#define MDMA_S0_X_MODIFY 0xFFC00E54 // MemDMA Stream 0 Source X Modify Register
#define MDMA_S0_Y_MODIFY 0xFFC00E5C // MemDMA Stream 0 Source Y Modify Register
#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 // MemDMA Stream 0 Source Current Descriptor Pointer Register
#define MDMA_S0_CURR_ADDR 0xFFC00E64 // MemDMA Stream 0 Source Current Address Register
#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 // MemDMA Stream 0 Source Current X Count Register
#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 // MemDMA Stream 0 Source Current Y Count Register
#define MDMA_S0_IRQ_STATUS 0xFFC00E68 // MemDMA Stream 0 Source Interrupt/Status Register
#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C // MemDMA Stream 0 Source Peripheral Map Register
//// Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF)
#define PPI_CONTROL 0xFFC01000 // PPI Control Register
#define PPI_STATUS 0xFFC01004 // PPI Status Register
#define PPI_COUNT 0xFFC01008 // PPI Transfer Count Register
#define PPI_DELAY 0xFFC0100C // PPI Delay Count Register
#define PPI_FRAME 0xFFC01010 // PPI Frame Length Register
//**********************************************************************************
// System MMR Register Bits
//******************************************************************************
// ********************* PLL AND RESET MASKS ************************
//// PLL_CTL Masks
#define PLL_CLKIN 0x00000000 // Pass CLKIN to PLL
#define PLL_CLKIN_DIV2 0x00000001 // Pass CLKIN/2 to PLL
#define PLL_OFF 0x00000002 // Shut off PLL clocks
#define STOPCK_OFF 0x00000008 // Core clock off
#define PDWN 0x00000020 // Put the PLL in a Deep Sleep state
#define BYPASS 0x00000100 // Bypass the PLL
//// PLL_DIV Masks
#define SCLK_DIV(x) (x) // SCLK = VCO / x
#define CCLK_DIV1 0x00000000 // CCLK = VCO / 1
#define CCLK_DIV2 0x00000010 // CCLK = VCO / 2
#define CCLK_DIV4 0x00000020 // CCLK = VCO / 4
#define CCLK_DIV8 0x00000030 // CCLK = VCO / 8
// SWRST Mask
#define SYSTEM_RESET 0x00000007 // Initiates a system software reset
// ************* SYSTEM INTERRUPT CONTROLLER MASKS *****************
// SIC_IAR0 Masks
#define P0_IVG(x) ((x)-7) // Peripheral #0 assigned IVG #x
#define P1_IVG(x) ((x)-7) << 0x4 // Peripheral #1 assigned IVG #x
#define P2_IVG(x) ((x)-7) << 0x8 // Peripheral #2 assigned IVG #x
#define P3_IVG(x) ((x)-7) << 0xC // Peripheral #3 assigned IVG #x
#define P4_IVG(x) ((x)-7) << 0x10 // Peripheral #4 assigned IVG #x
#define P5_IVG(x) ((x)-7) << 0x14 // Peripheral #5 assigned IVG #x
#define P6_IVG(x) ((x)-7) << 0x18 // Peripheral #6 assigned IVG #x
#define P7_IVG(x) ((x)-7) << 0x1C // Peripheral #7 assigned IVG #x
// SIC_IAR1 Masks
#define P8_IVG(x) ((x)-7) // Peripheral #8 assigned IVG #x
#define P9_IVG(x) ((x)-7) << 0x4 // Peripheral #9 assigned IVG #x
#define P10_IVG(x) ((x)-7) << 0x8 // Peripheral #10 assigned IVG #x
#define P11_IVG(x) ((x)-7) << 0xC // Peripheral #11 assigned IVG #x
#define P12_IVG(x) ((x)-7) << 0x10 // Peripheral #12 assigned IVG #x
#define P13_IVG(x) ((x)-7) << 0x14 // Peripheral #13 assigned IVG #x
#define P14_IVG(x) ((x)-7) << 0x18 // Peripheral #14 assigned IVG #x
#define P15_IVG(x) ((x)-7) << 0x1C // Peripheral #15 assigned IVG #x
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