initialization.asm

dsp转换USB通讯程序样例

#include "defBF531.h"
#include "BF531_USB_Head.h"

.extern _SPORT0_RX_ISR;

.extern Rx0_BufA,Tx0_BufA;

.section SECTION_Code2;

/*****************************************************************************
 Function:	Init_Sport													//
																			//
 Description:	Configure Sport0 for I2S mode, to transmit/receive data 
		to/from the AD1836. Configure Sport for external clocks and 
		framesyncs.													//
******************************************************************************/
.global Init_Sport0;
Init_Sport0:

	// Sport0 receive configuration
	// External CLK, External Frame sync, MSB first, Active Low, Late frame
	// 24-bit data, Secondary side enable, Stereo frame sync enable
	P0.H = HI(SPORT0_RCR1);
	P0.L = LO(SPORT0_RCR1);
	R0.L = RFSR | LRFS | RCKFE;
	//R0 = RFSR | RCKFE;
	W[ P0 ] = R0.L;
	ssync;
	
	P0.H = HI(SPORT0_RCR2);
	P0.L = LO(SPORT0_RCR2);
	//R0 = SLEN_16 | RSFSE | RRFST | RXSE;
	R0.L = SLEN_16 | RSFSE | RXSE;
	W[ P0 ] = R0.L;
	ssync;

	// Sport0,1 transmit configuration
	// External CLK, External Frame sync, MSB first, Active Low, Late frame
	// 24-bit data, Secondary side enable, Stereo frame sync enable

	P0.H = HI(SPORT0_TCR1);
	P0.L = LO(SPORT0_TCR1);
	R0.L = TFSR | LTFS | TCKFE;
	//R0 = TFSR | TCKFE;
	W[ P0 ] = R0.L;
	ssync;
	
	P0.H = HI(SPORT0_TCR2);
	P0.L = LO(SPORT0_TCR2);
	//R0 = SLEN_16 | TSFSE | TRFST | TXSE;
	R0.L = SLEN_16 | TSFSE | TXSE;
	W[ P0 ] = R0.L;
	ssync;
	RTS;
Init_Sport0.END:
/*****************************************************************************
 Function:	Init_DMA													//
																			//
 Description:	Initialize DMA1 in autobuffer mode to receive and DMA2 in	
				autobuffer mode to transmit									//
******************************************************************************/
.global Init_DMA_Sport0;
Init_DMA_Sport0:
	
//Set up DMA1 for Rx0 Pri-----------------------------------------
//start
	// Map DMA1 to Sport0 RX Primary
	P1.H = HI(DMA1_PERIPHERAL_MAP);
	P1.L = LO(DMA1_PERIPHERAL_MAP);
	R1.L = 0x1000;
	W[ P1 ] = R1.l;
	
	// Configure DMA1
	P1.H = HI(DMA1_CONFIG);
	P1.L = LO(DMA1_CONFIG);
	R1.L = WNR | WDSIZE_16 | DI_EN | FLOW_1 | DI_SEL |DMA2D;	
	W[ P1 ] = R1.L;
	
	// Start address of data buffer
	P1.H = HI(DMA1_START_ADDR);
	P1.L = LO(DMA1_START_ADDR);
	r1.H = Rx0_BufA;
	r1.L = Rx0_BufA;
	[ P1 ] = R1; 

	// DMA inner loop count
	P1.H = HI(DMA1_X_COUNT);
	P1.L = LO(DMA1_X_COUNT);
	R1.L = 4*FrameLength;	
	W[ P1 ] = R1.L; 

	// Inner loop address increment
	P1.H = HI(DMA1_X_MODIFY);
	P1.L = LO(DMA1_X_MODIFY);
	R1.L = 2;
	W[ P1 ] = R1.L; 
	
	// DMA outer loop count
	P1.H = HI(DMA1_Y_COUNT);
	P1.L = LO(DMA1_Y_COUNT);
	R1.L = 2;					//2 sub buffers
	W[ P1 ] = R1.L; 

	// Outer loop address increment
	P1.H = HI(DMA1_Y_MODIFY);
	P1.L = LO(DMA1_Y_MODIFY);
	R1.L = 2;					//offset from the end of the first
								//buffer to the start of the second buffer
	W[ P1 ] = R1.L; 
	
//end
//Set up DMA1 for Rx0 Pri-----------------------------------------
	
//Set up DMA2 for Tx0 Pri-----------------------------------------
//start
	// Map DMA2 to Sport0 TX Primary
	P1.L = LO(DMA2_PERIPHERAL_MAP);
	P1.H = HI(DMA2_PERIPHERAL_MAP);
	R1.L = 0x2000;
	W[ P1 ] = R1.l;
	
	// Configure DMA2
	P1.H = HI(DMA2_CONFIG);
	P1.L = LO(DMA2_CONFIG);
	R1.L = WDSIZE_16 | FLOW_1 | DI_SEL |DMA2D;	
	W[ P1 ] = R1.L;
	
	// Start address of data buffer
	P1.H = HI(DMA2_START_ADDR);
	P1.L = LO(DMA2_START_ADDR);
	r1.H = Tx0_BufA;
	r1.L = Tx0_BufA;
	[ P1 ] = R1; 

	// DMA inner loop count
	P1.H = HI(DMA2_X_COUNT);
	P1.L = LO(DMA2_X_COUNT);
	R1.L = 4*FrameLength;	
	W[ P1 ] = R1.L; 

	// Inner loop address increment
	P1.H = HI(DMA2_X_MODIFY);
	P1.L = LO(DMA2_X_MODIFY);
	R1.L = 2;
	W[ P1 ] = R1.L; 
	
	// DMA outer loop count
	P1.H = HI(DMA2_Y_COUNT);
	P1.L = LO(DMA2_Y_COUNT);
	R1.L = 2;					//2 sub buffers
	W[ P1 ] = R1.L; 

	// Outer loop address increment
	P1.H = HI(DMA2_Y_MODIFY);
	P1.L = LO(DMA2_Y_MODIFY);
	R1.L = 2;					//offset from the end of the first
								//buffer to the start of the second buffer
	W[ P1 ] = R1.L; 

//end
//Set up DMA2 for Tx0 Pri-----------------------------------------
	

	RTS;
Init_DMA_Sport0.END:

	
/*****************************************************************************
 Function:	Init_Interrupts												//
																			//
 Description:	Initialize Interrupt for Sport0 RX							
******************************************************************************/
.global Init_Interrupts;
Init_Interrupts:

	P0.L = LO(SIC_IAR1);
	P0.H = HI(SIC_IAR1);	
	R1.L = 0xff3f;		//Set Sport0 RX (DMA1) interrupt priority to 3 = IVG10
	R1.H = 0xf2ff;   	//Set Uart RX (DMA6) interrupt priority to 2 = IVG9
	[ P0 ] = R1;

	P0.L = LO(SIC_IMASK);
	P0.H = HI(SIC_IMASK);
	R1 = [ P0 ];
	//BITSET(R1, 14);		//Uart Rx unmask
	BITSET(R1, 9);		//SPort0 Rx unmask
	[ P0 ] = R1;
	
	// Remap the vector table pointer from the default __I9HANDLER 
	// to the new _UartRxISR interrupt service routine
	P0.L = LO(EVT9);
	P0.H = HI(EVT9);
//	R0.l = _UartRxIsr;
//	R0.h = _UartRxIsr;
	[ P0 ] = R0;

	
	// Remap the vector table pointer from the default __I10HANDLER 
	// to the new _SPORT0_RX_ISR interrupt service routine
	P0.L = LO(EVT10);
	P0.H = HI(EVT10);
	R0.l = _SPORT0_RX_ISR;
	R0.h = _SPORT0_RX_ISR;
	[ P0 ] = R0;
	
		
	P0.L = LO(IMASK);
	P0.H = HI(IMASK);
	R7 = [ P0 ];
	R1.H = 0;
	R1.L = 0x0400;    //IVG10 interrupt enable
	R7 = R7 | R1;
	[ P0 ] = R7;      //Reserve residual interrupt bit
	
	
	RTS;
Init_Interrupts.END:
	
/*****************************************************************************
 Function:	Enable_DMA_Sport											//
																			//
 Description:	Enable DMA1, DMA2, Sport0 TX and Sport0 RX					
******************************************************************************/
.global Enable_DMA_Sport0;
Enable_DMA_Sport0:

	// Enable DMA2
	P1.H = HI(DMA2_CONFIG);
	P1.L = LO(DMA2_CONFIG);
	R1.L = W[ P1 ];
	BITSET(R1,DMAEN_P);
	W[ P1 ] = R1.L; 

	// Enable DMA1
	P1.H = HI(DMA1_CONFIG);
	P1.L = LO(DMA1_CONFIG);
	R1.L = W[ P1 ];
	BITSET(R1,DMAEN_P);
	W[ P1 ] = R1.L; 
	
	// ENABLE SPORT0 TX
	P1.H = HI(SPORT0_TCR1);
	P1.L = LO(SPORT0_TCR1);
	R1.L = W[ P1 ];
	BITSET(R1,0);
	W[ P1 ] = R1; 

	// ENABLE SPORT0 RX
	P1.H = HI(SPORT0_RCR1);
	P1.L = LO(SPORT0_RCR1);
	R1.L = W[ P1 ];
	BITSET(R1,0);
	W[ P1 ] = R1; 

	RTS;
Enable_DMA_Sport0.END:
	
/*****************************************************************************
 Function:	Disable_DMA_Sport											//
																			//
 Description:	DIsable DMA1, DMA2, Sport0 TX and Sport0 RX					
******************************************************************************/
.global Disable_DMA_Sport0;
Disable_DMA_Sport0:

	// Disable DMA2
	P1.H = HI(DMA2_CONFIG);
	P1.L = LO(DMA2_CONFIG);
	R1.L = W[ P1 ];
	BITCLR(R1,DMAEN_P);
	W[ P1 ] = R1.L; 

	// Disable DMA1
	P1.H = HI(DMA1_CONFIG);
	P1.L = LO(DMA1_CONFIG);
	R1.L = W[ P1 ];
	BITCLR(R1,DMAEN_P);
	W[ P1 ] = R1.L; 
	
	// Disable SPORT0 TX
	P1.H = HI(SPORT0_TCR1);
	P1.L = LO(SPORT0_TCR1);
	R1.L = W[ P1 ];
	BITCLR(R1,0);
	W[ P1 ] = R1; 

	// Disable SPORT0 RX
	P1.H = HI(SPORT0_RCR1);
	P1.L = LO(SPORT0_RCR1);
	R1.L = W[ P1 ];
	BITCLR(R1,0);
	W[ P1 ] = R1; 
	
	RTS;
Disable_DMA_Sport0.END:
	
/*****************************************************************************
 Function:	Init_FLG											//
																			//
 Description:	Enable DMA1, DMA2, Sport0 TX and Sport0 RX					
******************************************************************************/	
.global Init_FLG;
Init_FLG:
    [ --SP ] = RETS;
	
	p0.l = lo(FIO_DIR);
	p0.h = hi(FIO_DIR);
	r0.l = 0xbf14;
	w[p0] = r0.l;
	ssync;
	
	p0.l=lo(FIO_INEN);
	p0.h=hi(FIO_INEN);
	r0.l = 0x00e0;
	w[p0] = r0.l;
	ssync;
	
	//all PF up
    p0.l = lo(FIO_FLAG_D);
	p0.h = hi(FIO_FLAG_D);
	r1.l = 0xffff;
	w[p0] = r1.l;
	ssync;
	
	RETS = [ SP++ ];
	RTS;    
Init_FLG.END: 
    
    
	
/*****************************************************************************
 Function:	MsDelay
																			//
 Description: delay time in r0.l, p2 to be destroied	
******************************************************************************/	
.global MsDelay;
MsDelay:
    [ --SP ] = RETS;
    [ --SP ]=lc0;
	[ --SP ]=lt0;
	[ --SP ]=lb0;
	[ --SP ]=r0;
	[ --SP ]=p2;
	
#ifndef SoftSimu		
	r0.h=0;
	r0=r0<<13;
	p2 = r0; nop;nop;nop;nop;
	lsetup(MsDelayLoop_start, MsDelayLoop_end) lc0=p2;
	MsDelayLoop_start: 
	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
	nop;nop;nop;nop;nop;nop;nop;
	MsDelayLoop_end:
	nop;
#endif	

	p2=[ SP++ ];
	r0=[ SP++ ];
	lb0=[ SP++ ];
	lt0=[ SP++ ];
	lc0=[ SP++ ];
	RETS = [ SP++ ];
	rts;
MsDelay.end:
/*****************************************************************************
 Function:	UsDelay
																			//
 Description: delay time in r0.l, p2 to be destroied	
******************************************************************************/	
.global UsDelay;
UsDelay:
    [ --SP ] = RETS;
#ifndef SoftSimu		
	r0.h=0;
	r0=r0<<4;
	p2 = r0; nop;nop;nop;nop;
	lsetup(UsDelayLoop_start, UsDelayLoop_end) lc0=p2;
	UsDelayLoop_start: 
	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
	nop;nop;nop;nop;
	UsDelayLoop_end:
	nop;
#endif	
	RETS = [ SP++ ];
	rts;
UsDelay.end:



/*****************************************************************************
 Function:	InitVar
																			//
 Description: