uhc124.h

TDI的USB HOST芯片UHC124的编程手册和固件驱动源代码

/*
	UH124.H: UH124 symbolic definitions

(C) Copyright TransDimension, Inc.  All rights reserved.             
                                                                   
Modification history
====================
20Nov1999 Original Release
31Jan2001 Modified, JW

*/

#ifndef UH124_H

#define UH124_H

#include "types.h"

/*	memory map */

#define MREG_BASE		0x0	    /* control registers (16 bytes) */
#define MREG_LEN		16	    /* size of control registers */
#define MXFD_BASE		0x400	/* XD memory (256 bytes) */
#define MXFD_LEN		256	    /* size of xd memory */
#define MDAT_BASE		0x800	/* data memory (2048 bytes) */
#define MDAT_LEN		2048

#define MMAG_RST		0x700	/* magic reset */

/*	offset of control registers */

#define UhcControl		0	/* control register */
#define UhcTransSel		2	/* transaction select register */
#define UhcTransDone	4	/* transaction done register */
#define UhcIntpStatus	6	/* interrupt status register */
#define UhcIntpEnb		7	/* interrupt enable register */
#define UhcFmInterval	8	/* frame interval register */
#define UhcFmRemaining	10	/* frame remaining register */
#define UhcFmNumber		12	/* frame number register */
#define UhcMaxOverhead	14	/* maximum overhead register */
#define UhcMagicNumber	15	/* magic number register */

/*	UhcControl register bit masks */

#define CtlPwrSav		    0x80	/* power save mode on */
#define CtlReserved		    0x40	/* reserved */
#define CtlSoftReset	    0x20	/* soft reset */
#define CtlUSBReset		    0x10	/* usb reset */
#define CtlUSBSuspend		0x8	    /* usb suspend */
#define CtlUSBResume		0x4	    /* usb resume */
#define CtlUSBOperational	0x2	    /* usb operational */
#define CtlBatchOn		    0x1	    /* batch dispatch */
#define CtlUSBState		    0x1e	/* system state */ 

/*	UhcIntpEnb and UhcIntpStatus bit masks and constants */

#define IntpBatchStop		0x80	/* batch stopped */
#define IntpBatchCompl		0x40	/* batch completed */

#define IntpReserved		0x30	/* reserved */
#define IntpHostError		0x8	    /* host error */
#define IntpResumeDetect	0x4	    /* resume detected */
#define IntpPortChange		0x2	    /* root hub status change */
#define IntpStartOfFrame	0x1	    /* start of frame */

#define INTP_MASK		~(IntpReserved)

/*	UhcMagicNumber constants */

#define MagicNumber		0xdb	/* retrieved from reg */
#define MagicKey1		0x55	/* unlock sequence key 1 */
#define MagicKey2		0xaa	/* unlock sequence key 2 */

/*	transaction descriptors */

#define NXDS			16	/* number of xd's */

/*	transaction descriptor field offsets */

#define XDControl		0x0	/* transaction control */
#define XDStatus		0x1	/* transaction status */
#define XDDevAddr		0x2	/* device address */
#define XDEpNum			0x3	/* endpoint number */
#define XDBufAddr		0x4	/* data buffer address */
#define XDBufLen		0x6	/* buffer length */
#define XDXferCnt		0x8	/* transfer count */

/*	XDControl bit masks and constants */
 
#define XDCtlStop		0xe0	/* stop control bit mask */
#define XDCtlStopSucc	0x80	/* stop on succ xact */ 
#define XDCtlStopNak	0x40	/* stop on nak */
#define XDCtlStopErr	0x20	/* stop on failed xact */

#define XDCtlSpd		0x10	/* device speed */
#define XDCtlIso		0x8	    /* isochronous transaction */
#define XDCtlSeq		0x4	    /* output data sequence */
#define XDCtlPid		0x3	    /* xact pid */

#define XDCTL_SETUP		0x0	    /* setup pid */
#define XDCTL_IN		0x2	    /* in pid */
#define XDCTL_OUT		0x1	    /* out pid */
#define XDCTL_DATA1		0x4	    /* data1 packet */
#define XDCTL_DATA0		0x0	    /* data0 packet */
#define XDCTL_ISO		0x8	    /* iso xact */
#define XDCTL_LSPD		0x10	/* low speed xact */
#define XDCTL_FSPD		0x0	    /* high speed xact */

/*	XDStatus bit masks and constants */

#define XDStsStall		0x40	/* stall */
#define XDStsError		0x20	/* error */
#define XDStsOverflow	0x10	/* overflow */
#define XDStsTimeout	0x8	    /* timeout */
#define XDStsNak		0x4	    /* NAK */
#define XDStsSeq		0x2	    /* in data sequence */
#define XDStsAck		0x1	    /* ACK */

/*	root hub */

#define NPORTS			4	    /* number of ports */

#endif