📄 traffic.rpt
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-- Equation name is '~1957~1', location is LC074, type is buried.
-- synthesized logic cell
_LC074 = LCELL( _EQ045 $ GND);
_EQ045 = ew & !SS00 & !SS01 & !SS02 & !start
# en & !SS00 & !SS01 & !SS02 & !start
# !sn & !SS00 & !SS01 & !SS02 & !start
# !en & ew & !sn;
-- Node name is '~1969~1'
-- Equation name is '~1969~1', location is LC082, type is buried.
-- synthesized logic cell
_LC082 = LCELL( _EQ046 $ GND);
_EQ046 = clk & t10 & t11 & !t12 & t13 & t14 & !t15 & !t16
# clk & !t11 & t12 & t13 & t14 & !t15 & !t16
# ew & !_LC062 & sn & !SS00 & !SS01 & !SS02 & !start
# !ew & !_LC062 & !sn & !SS00 & !SS01 & !SS02 & !start
# en & !_LC062 & !SS00 & !SS01 & !SS02 & !start;
-- Node name is '~1987~1'
-- Equation name is '~1987~1', location is LC079, type is buried.
-- synthesized logic cell
_LC079 = LCELL( _EQ047 $ !start);
_EQ047 = !en & ew & !sn & !start
# !en & !ew & sn & !start
# SS02 & !start & _X015
# !SS01 & !SS02 & !start;
_X015 = EXP(!SS00 & !SS01);
-- Node name is '~1993~1'
-- Equation name is '~1993~1', location is LC068, type is buried.
-- synthesized logic cell
_LC068 = LCELL( _EQ048 $ GND);
_EQ048 = !en & ew & !sn
# !en & !ew & sn
# !SS02 & !start;
-- Node name is '~1999~1'
-- Equation name is '~1999~1', location is LC076, type is buried.
-- synthesized logic cell
_LC076 = LCELL( _EQ049 $ !start);
_EQ049 = !en & ew & !sn & !start
# !en & !ew & sn & !start
# !SS02 & !start & _X014
# !SS00 & !SS01 & !start;
_X014 = EXP( SS00 & SS01);
-- Node name is '~3382~1'
-- Equation name is '~3382~1', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ050 $ GND);
_EQ050 = sn & !SS10 & !SS11 & SS12 & !start
# en & !SS10 & !SS11 & SS12 & !start
# !ew & !SS10 & !SS11 & SS12 & !start
# !en & !ew & sn;
-- Node name is '~3664~1'
-- Equation name is '~3664~1', location is LC038, type is buried.
-- synthesized logic cell
_LC038 = LCELL( _EQ051 $ VCC);
_EQ051 = !SS10 & !SS11 & SS12 & _X016
# !en & !ew & sn
# start & _X016;
_X016 = EXP(!en & ew & !sn);
-- Node name is '~3669~1'
-- Equation name is '~3669~1', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ052 $ GND);
_EQ052 = !t10 & !t11 & !t12 & t13 & !t14 & !t15 & t16
# t11 & t12 & !t13 & !t14 & !t15 & t16;
-- Node name is '~3673~1'
-- Equation name is '~3673~1', location is LC036, type is buried.
-- synthesized logic cell
_LC036 = LCELL( _EQ053 $ !start);
_EQ053 = !en & !ew & sn & !start
# !en & ew & !sn & !start
# !SS12 & !start & _X017
# !SS10 & !SS11 & !start;
_X017 = EXP( SS10 & SS11);
-- Node name is '~3679~1'
-- Equation name is '~3679~1', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ054 $ GND);
_EQ054 = sn & !SS10 & !SS11 & SS12 & !start
# en & !SS10 & !SS11 & SS12 & !start
# !ew & !SS10 & !SS11 & SS12 & !start
# !en & !ew & sn;
-- Node name is '~3700~1'
-- Equation name is '~3700~1', location is LC045, type is buried.
-- synthesized logic cell
_LC045 = LCELL( _EQ055 $ GND);
_EQ055 = !en & ew & !sn
# !en & !ew & sn
# SS12 & !start;
-- Node name is '~3703~1'
-- Equation name is '~3703~1', location is LC041, type is buried.
-- synthesized logic cell
_LC041 = LCELL( _EQ056 $ !start);
_EQ056 = !en & !ew & sn & !start
# !en & ew & !sn & !start
# !SS12 & !start & _X017
# !SS10 & !SS11 & !start;
_X017 = EXP( SS10 & SS11);
-- Node name is '~3709~1'
-- Equation name is '~3709~1', location is LC048, type is buried.
-- synthesized logic cell
_LC048 = LCELL( _EQ057 $ !start);
_EQ057 = !en & !ew & sn & !start
# !en & ew & !sn & !start
# SS10 & SS11 & !start
# SS12 & !start;
-- Node name is '~3718~1'
-- Equation name is '~3718~1', location is LC046, type is buried.
-- synthesized logic cell
_LC046 = LCELL( _EQ058 $ GND);
_EQ058 = !en & ew & !sn
# !en & !ew & sn
# SS12 & !start
# !SS11 & !start;
-- Node name is '~3721~1'
-- Equation name is '~3721~1', location is LC044, type is buried.
-- synthesized logic cell
_LC044 = LCELL( _EQ059 $ GND);
_EQ059 = ew & sn & SS10 & !SS12 & !start
# !ew & !sn & SS10 & !SS12 & !start
# en & SS10 & !SS12 & !start;
-- Node name is '~3883~1'
-- Equation name is '~3883~1', location is LC070, type is buried.
-- synthesized logic cell
_LC070 = LCELL( _EQ060 $ VCC);
_EQ060 = !SS10 & !SS11 & SS12 & !t10 & !t11 & !t12 & t13 & !t14 & !t15 &
t16 & _X016
# !SS10 & !SS11 & SS12 & t11 & t12 & !t13 & !t14 & !t15 & t16 &
_X016
# !en & !ew & _LC050 & sn
# _LC050 & start & _X016
# !_LC038 & !_LC050;
_X016 = EXP(!en & ew & !sn);
-- Node name is '~3887~1'
-- Equation name is '~3887~1', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ061 $ GND);
_EQ061 = !t10 & !t11 & !t12 & t13 & !t14 & t15 & t16
# t11 & t12 & !t13 & !t14 & t15 & t16;
-- Node name is '~3892~1'
-- Equation name is '~3892~1', location is LC034, type is buried.
-- synthesized logic cell
_LC034 = LCELL( _EQ062 $ _EQ063);
_EQ062 = !en & !ew & _LC050 & sn & _X018 & _X019 & _X020
# !en & ew & _LC050 & !sn & _X018 & _X019 & _X020
# _LC050 & !SS11 & !SS12 & _X018 & _X019 & _X020
# _LC050 & !SS10 & !SS12 & _X018 & _X019 & _X020;
_X018 = EXP( _LC050 & start);
_X019 = EXP( _LC050 & !SS10 & !SS11);
_X020 = EXP(!_LC036 & !_LC050);
_EQ063 = _X018 & _X019 & _X020;
_X018 = EXP( _LC050 & start);
_X019 = EXP( _LC050 & !SS10 & !SS11);
_X020 = EXP(!_LC036 & !_LC050);
-- Node name is '~3898~1'
-- Equation name is '~3898~1', location is LC039, type is buried.
-- synthesized logic cell
_LC039 = LCELL( _EQ064 $ GND);
_EQ064 = _LC050 & sn & !SS10 & !SS11 & SS12 & !start
# en & _LC050 & !SS10 & !SS11 & SS12 & !start
# !ew & _LC050 & !SS10 & !SS11 & SS12 & !start
# !en & !ew & _LC050 & sn
# _LC042 & !_LC050;
-- Node name is '~3922~1'
-- Equation name is '~3922~1', location is LC043, type is buried.
-- synthesized logic cell
_LC043 = LCELL( _EQ065 $ _EQ066);
_EQ065 = !en & !ew & _LC050 & sn & _X018 & _X019 & _X021
# !en & ew & _LC050 & !sn & _X018 & _X019 & _X021
# _LC050 & !SS11 & !SS12 & _X018 & _X019 & _X021
# _LC050 & !SS10 & !SS12 & _X018 & _X019 & _X021;
_X018 = EXP( _LC050 & start);
_X019 = EXP( _LC050 & !SS10 & !SS11);
_X021 = EXP(!_LC041 & !_LC050);
_EQ066 = _X018 & _X019 & _X021;
_X018 = EXP( _LC050 & start);
_X019 = EXP( _LC050 & !SS10 & !SS11);
_X021 = EXP(!_LC041 & !_LC050);
-- Node name is '~3940~1'
-- Equation name is '~3940~1', location is LC063, type is buried.
-- synthesized logic cell
_LC063 = LCELL( _EQ067 $ GND);
_EQ067 = ew & sn & SS10 & !SS12 & !start & !t10 & !t11 & !t12 & t13 &
!t14 & !t15 & t16
# ew & sn & SS10 & !SS12 & !start & t11 & t12 & !t13 & !t14 &
!t15 & t16
# !ew & _LC050 & !sn & SS10 & !SS12 & !start
# en & _LC050 & SS10 & !SS12 & !start
# _LC044 & !_LC050;
-- Node name is '~3946~1'
-- Equation name is '~3946~1', location is LC078, type is buried.
-- synthesized logic cell
_LC078 = LCELL( _EQ068 $ GND);
_EQ068 = clk & !t10 & !t11 & !t12 & t13 & !t14 & !t15 & t16
# clk & t11 & t12 & !t13 & !t14 & !t15 & t16
# ew & !_LC050 & sn & !SS10 & SS11 & !SS12 & !start
# !ew & !_LC050 & !sn & !SS10 & SS11 & !SS12 & !start
# en & !_LC050 & !SS10 & SS11 & !SS12 & !start;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X016 occurs in LABs C, E
Project Information e:\shiyan\eda\trafficlight1\traffic.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:03
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,170K
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