traffic.rpt

EDA仿真程序

        | +--- LC19 t15
        | | +- LC17 t16
        | | | 
        | | |   Other LABs fed by signals
        | | |   that feed LAB 'B'
LC      | | | | A B C D E F |     Logic cells that feed LAB 'B':
LC19 -> - * - | - * - * * * | <-- t15
LC17 -> - - * | - * - * * * | <-- t16

Pin
67   -> - - - | - - - - * * | <-- clk
12   -> * * * | - * * * * * | <-- en
13   -> * * * | - * * * * * | <-- start
LC54 -> - * - | - * - - - - | <-- |LPM_ADD_SUB:98|addcore:adder|result_node5
LC64 -> - - * | - * - - - - | <-- |LPM_ADD_SUB:98|addcore:adder|result_node6
LC33 -> * - - | - * - * * * | <-- t10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           e:\shiyan\eda\trafficlight1\traffic.rpt
traffic

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC35 SN_L2
        | +----------------------------- LC37 SN_M0
        | | +--------------------------- LC40 SN_P1
        | | | +------------------------- LC33 t10
        | | | | +----------------------- LC47 ~3382~1
        | | | | | +--------------------- LC38 ~3664~1
        | | | | | | +------------------- LC36 ~3673~1
        | | | | | | | +----------------- LC42 ~3679~1
        | | | | | | | | +--------------- LC45 ~3700~1
        | | | | | | | | | +------------- LC41 ~3703~1
        | | | | | | | | | | +----------- LC48 ~3709~1
        | | | | | | | | | | | +--------- LC46 ~3718~1
        | | | | | | | | | | | | +------- LC44 ~3721~1
        | | | | | | | | | | | | | +----- LC34 ~3892~1
        | | | | | | | | | | | | | | +--- LC39 ~3898~1
        | | | | | | | | | | | | | | | +- LC43 ~3922~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'C':
LC47 -> - * - - - - - - - - - - - - - - | - - * - - - | <-- ~3382~1
LC36 -> - - - - - - - - - - - - - * - - | - - * * - - | <-- ~3673~1
LC42 -> - * - - - - - - - - - - - - * - | - - * - - - | <-- ~3679~1
LC41 -> - - - - - - - - - - - - - - - * | - - * * - - | <-- ~3703~1
LC46 -> * - - - - - - - - - - - - - - - | - - * - - - | <-- ~3718~1
LC39 -> - * - - - - - - - - - - - - - - | - - * - - - | <-- ~3898~1

Pin
67   -> - - - - - - - - - - - - - - - - | - - - - * * | <-- clk
12   -> * - * * * * * * * * * * * * * * | - * * * * * | <-- en
10   -> * - * - * * * * * * * * * * * * | - - * * * * | <-- ew
9    -> * - * - * * * * * * * * * * * * | - - * * * * | <-- sn
13   -> * - * * * * * * * * * * * * * * | - * * * * * | <-- start
LC58 -> * - * - * * * * * * * * * * * * | - - * * * - | <-- SS12
LC66 -> * - * - * * * * - * * * - * * * | - - * * * - | <-- SS11
LC52 -> - - * - * * * * - * * - * * * * | - - * * * - | <-- SS10
LC50 -> - * - - - - - - - - - - - * * * | - - * * * - | <-- ~3669~1
LC55 -> * * - - - - - - - - - - - - - - | - - * * * - | <-- ~3887~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           e:\shiyan\eda\trafficlight1\traffic.rpt
traffic

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC54 |LPM_ADD_SUB:98|addcore:adder|result_node5
        | +----------------------------- LC64 |LPM_ADD_SUB:98|addcore:adder|result_node6
        | | +--------------------------- LC59 SN_L1
        | | | +------------------------- LC61 SN_M1
        | | | | +----------------------- LC56 SN_R1
        | | | | | +--------------------- LC57 SN_R2
        | | | | | | +------------------- LC51 t12
        | | | | | | | +----------------- LC53 t13
        | | | | | | | | +--------------- LC49 t14
        | | | | | | | | | +------------- LC58 SS12
        | | | | | | | | | | +----------- LC52 SS10
        | | | | | | | | | | | +--------- LC62 ~1671~1
        | | | | | | | | | | | | +------- LC60 ~1946~1
        | | | | | | | | | | | | | +----- LC50 ~3669~1
        | | | | | | | | | | | | | | +--- LC55 ~3887~1
        | | | | | | | | | | | | | | | +- LC63 ~3940~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'D':
LC51 -> * * - * * * * * * * * * * * * * | - - - * * * | <-- t12
LC53 -> * * - * * * - * * * * * * * * * | - - - * * * | <-- t13
LC49 -> * * - * * * - - * * * * * * * * | - - - * * * | <-- t14
LC58 -> - - * - - * - - - * * - - - - * | - - * * * - | <-- SS12
LC52 -> - - * - - - - - - * * - - - - * | - - * * * - | <-- SS10
LC50 -> - - * * * - - - - - - - - - - * | - - * * * - | <-- ~3669~1
LC55 -> - - * * * * - - - - - - - - - - | - - * * * - | <-- ~3887~1
LC63 -> - - * - - - - - - - - - - - - - | - - - * - - | <-- ~3940~1

Pin
67   -> - - - - - - - - - - - - - - - - | - - - - * * | <-- clk
12   -> - - * - - * * * * - - - - - - * | - * * * * * | <-- en
10   -> - - * - - * - - - - - - - - - * | - - * * * * | <-- ew
9    -> - - * - - * - - - - - - - - - * | - - * * * * | <-- sn
13   -> - - * - - * * * * * * - - - - * | - * * * * * | <-- start
LC33 -> * * - * * * * * * * * * * * * * | - * - * * * | <-- t10
LC24 -> * * - * * * * * * * * * * * * * | - - - * * * | <-- t11
LC19 -> * * - * * * - - - * * * * * * * | - * - * * * | <-- t15
LC17 -> - * - * * * - - - * * * * * * * | - * - * * * | <-- t16
LC66 -> - - - - - - - - - * * - - - - - | - - * * * - | <-- SS11
LC36 -> - - - * - - - - - - - - - - - - | - - * * - - | <-- ~3673~1
LC45 -> - - - - - * - - - - - - - - - - | - - - * - - | <-- ~3700~1
LC41 -> - - - - * - - - - - - - - - - - | - - * * - - | <-- ~3703~1
LC44 -> - - * - - - - - - - - - - - - * | - - - * - - | <-- ~3721~1
LC34 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- ~3892~1
LC43 -> - - - - * - - - - - - - - - - - | - - - * - - | <-- ~3922~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           e:\shiyan\eda\trafficlight1\traffic.rpt
traffic

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC77 EW_L2
        | +----------------------------- LC80 EW_P1
        | | +--------------------------- LC73 EW_R0
        | | | +------------------------- LC65 SN_L0
        | | | | +----------------------- LC67 SN_M2
        | | | | | +--------------------- LC69 SN_P0
        | | | | | | +------------------- LC72 SN_R0
        | | | | | | | +----------------- LC66 SS11
        | | | | | | | | +--------------- LC75 ~1504~1
        | | | | | | | | | +------------- LC71 ~1702~1
        | | | | | | | | | | +----------- LC74 ~1957~1
        | | | | | | | | | | | +--------- LC79 ~1987~1
        | | | | | | | | | | | | +------- LC68 ~1993~1
        | | | | | | | | | | | | | +----- LC76 ~1999~1
        | | | | | | | | | | | | | | +--- LC70 ~3883~1
        | | | | | | | | | | | | | | | +- LC78 ~3946~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'E':
LC66 -> - - - * - * - * - - - - - - * * | - - * * * - | <-- SS11
LC79 -> - - * - - - - - - - - - - - - - | - - - - * - | <-- ~1987~1
LC68 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- ~1993~1
LC70 -> - - - - * - - - - - - - - - - - | - - - - * - | <-- ~3883~1
LC78 -> - - - * - - - - - - - - - - - - | - - - - * - | <-- ~3946~1

Pin
67   -> - - * - - * * - - - - - - - - * | - - - - * * | <-- clk
12   -> * * - * - * - - * * * * * * * * | - * * * * * | <-- en
10   -> * * - * - * - - * * * * * * * * | - - * * * * | <-- ew
9    -> * * - * - * - - * * * * * * * * | - - * * * * | <-- sn
13   -> * * - * - * - * * * * * * * * * | - * * * * * | <-- start
LC33 -> * - * * * * * * - - - - - - * * | - * - * * * | <-- t10
LC24 -> * - * * * * * * - - - - - - * * | - - - * * * | <-- t11
LC51 -> * - * * * * * * - - - - - - * * | - - - * * * | <-- t12
LC53 -> * - * * * * * * - - - - - - * * | - - - * * * | <-- t13
LC49 -> * - * * * * * * - - - - - - * * | - - - * * * | <-- t14
LC19 -> * - * * * * * * - - - - - - * * | - * - * * * | <-- t15
LC17 -> * - * * * * * * - - - - - - * * | - * - * * * | <-- t16
LC83 -> * * - - - - - - * * * * * * - - | - - - - * * | <-- SS02
LC90 -> - * - - - - - - * * * * - * - - | - - - - * * | <-- SS01
LC93 -> - * - - - - - - * - * * - * - - | - - - - * * | <-- SS00
LC58 -> - - - * - * - * - - - - - - * * | - - * * * - | <-- SS12
LC52 -> - - - * - * - * - - - - - - * * | - - * * * - | <-- SS10
LC60 -> * - * - - - - - - - - - - - - - | - - - - * * | <-- ~1946~1
LC38 -> - - - - * - - - - - - - - - * - | - - - - * - | <-- ~3664~1
LC50 -> - - - * * - * - - - - - - - * * | - - * * * - | <-- ~3669~1
LC48 -> - - - - - - * - - - - - - - - - | - - - - * - | <-- ~3709~1
LC55 -> - - - * * * * - - - - - - - - - | - - * * * - | <-- ~3887~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           e:\shiyan\eda\trafficlight1\traffic.rpt
traffic

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                         Logic cells placed in LAB 'F'
        +------------------------------- LC92 EW_L0
        | +----------------------------- LC84 EW_L1
        | | +--------------------------- LC86 EW_M0
        | | | +------------------------- LC89 EW_M1
        | | | | +----------------------- LC96 EW_M2
        | | | | | +--------------------- LC88 EW_P0
        | | | | | | +------------------- LC94 EW_R1
        | | | | | | | +----------------- LC81 EW_R2
        | | | | | | | | +--------------- LC83 SS02
        | | | | | | | | | +------------- LC90 SS01
        | | | | | | | | | | +----------- LC93 SS00
        | | | | | | | | | | | +--------- LC87 ~1423~1
        | | | | | | | | | | | | +------- LC85 ~1432~1
        | | | | | | | | | | | | | +----- LC95 ~1441~1
        | | | | | | | | | | | | | | +--- LC91 ~1477~1
        | | | | | | | | | | | | | | | +- LC82 ~1969~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'F':
LC83 -> * - - - - * - * * * * * * * * * | - - - - * * | <-- SS02
LC90 -> * - - - - * - * * * * * * * * * | - - - - * * | <-- SS01
LC93 -> * - - - - * - - * * * * * * * * | - - - - * * | <-- SS00
LC87 -> - - - - * - - - - - - - - - - - | - - - - - * | <-- ~1423~1
LC85 -> - - - * - - - - - - - - - - - - | - - - - - * | <-- ~1432~1
LC95 -> - - * - - - - - - - - - - - - - | - - - - - * | <-- ~1441~1
LC91 -> - - - - - - * - - - - - - - - - | - - - - - * | <-- ~1477~1
LC82 -> - - - - - * - - - - - - - - - - | - - - - - * | <-- ~1969~1

Pin
67   -> * - - - - - - - - - - - - - - * | - - - - * * | <-- clk
12   -> * - - - - * - * - - - * * * * * | - * * * * * | <-- en
10   -> * - - - - * - * - - - * * * * * | - - * * * * | <-- ew
9    -> * - - - - * - * - - - * * * * * | - - * * * * | <-- sn
13   -> * - - - - * - * * * * * * * * * | - * * * * * | <-- start
LC33 -> * * * * * * * * * * * - - - - * | - * - * * * | <-- t10
LC24 -> * * * * * * * * * * * - - - - * | - - - * * * | <-- t11
LC51 -> * * * * * * * * * * * - - - - * | - - - * * * | <-- t12
LC53 -> * * * * * * * * * * * - - - - * | - - - * * * | <-- t13
LC49 -> * * * * * * * * * * * - - - - * | - - - * * * | <-- t14
LC19 -> * * * * * * * * * * * - - - - * | - * - * * * | <-- t15
LC17 -> * * * * * * * * * * * - - - - * | - * - * * * | <-- t16
LC75 -> - * - - - - - - - - - - - - - - | - - - - - * | <-- ~1504~1
LC62 -> - * * * * * * - - - - - - - - * | - - - - - * | <-- ~1671~1
LC71 -> - - - - - - - * - - - - - - - - | - - - - - * | <-- ~1702~1
LC60 -> * * * * * * * * - - - - - - - - | - - - - * * | <-- ~1946~1
LC74 -> - - * - - - - - - - - - - - - - | - - - - - * | <-- ~1957~1
LC76 -> - * - - - - - - - - - - - - - - | - - - - - * | <-- ~1999~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           e:\shiyan\eda\trafficlight1\traffic.rpt
traffic

** EQUATIONS **

clk      : INPUT;
en       : INPUT;
ew       : INPUT;
sn       : INPUT;
start    : INPUT;

-- Node name is 'EW_L0' 
-- Equation name is 'EW_L0', location is LC092, type is output.
 EW_L0   = LCELL( _EQ001 $  GND);
  _EQ001 =  clk & !t10 & !t11 & !t12 &  t13 & !t14 &  t15 &  t16
         #  clk &  t11 &  t12 & !t13 & !t14 &  t15 &  t16
         #  ew & !_LC060 &  sn & !SS00 & !SS01 &  SS02 & !start
         # !ew & !_LC060 & !sn & !SS00 & !SS01 &  SS02 & !start
         #  en & !_LC060 & !SS00 & !SS01 &  SS02 & !start;

-- Node name is 'EW_L1' 
-- Equation name is 'EW_L1', location is LC084, type is output.
 EW_L1   = LCELL( _EQ002 $  GND);
  _EQ002 = !_LC062 &  _LC075 & !t10 & !t11 & !t12 &  t13 & !t14 &  t15 &  t16
         # !_LC062 &  _LC075 &  t11 &  t12 & !t13 & !t14 &  t15 &  t16
         # !_LC060 &  _LC076;

-- Node name is 'EW_L2' 
-- Equation name is 'EW_L2', location is LC077, type is output.
 EW_L2   = LCELL( _EQ003 $  GND);
  _EQ003 = !en &  ew & !sn & !t10 & !t11 & !t12 &  t13 & !t14 &  t15 &  t16
         # !en &  ew & !sn &  t11 &  t12 & !t13 & !t14 &  t15 &  t16
         # !en & !ew &  _LC060 &  sn
         #  _LC060 & !SS02 & !start
         # !_LC060 &  _LC068;

-- Node name is 'EW_M0' 
-- Equation name is 'EW_M0', location is LC086, type is output.
 EW_M0   = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC060 &  _LC095 &  t10 &  t11 & !t12 &  t13 &  t14 & !t15 & !t16
         #  _LC060 &  _LC095 & !t11 &  t12 &  t13 &  t14 & !t15 & !t16
         #  _LC060 & !_LC062 &  _LC095
         # !_LC060 &  _LC074;

-- Node name is 'EW_M1' 
-- Equation name is 'EW_M1', location is LC089, type is output.
 EW_M1   = LCELL( _EQ005 $  GND);
  _EQ005 = !_LC062 &  _LC085 & !t10 & !t11 & !t12 &  t13 & !t14 &  t15 &  t16
         # !_LC062 &  _LC085 &  t11 &  t12 & !t13 & !t14 &  t15 &  t16
         # !_LC060 &  _LC085;

-- Node name is 'EW_M2' 
-- Equation name is 'EW_M2', location is LC096, type is output.
 EW_M2   = LCELL( _EQ006 $  GND);
  _EQ006 = !_LC062 &  _LC087 & !t10 & !t11 & !t12 &  t13 & !t14 &  t15 &  t16
         # !_LC062 &  _LC087 &  t11 &  t12 & !t13 & !t14 &  t15 &  t16
         # !_LC060 &  _LC087;