📄 traffic.rpt
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Project Information e:\shiyan\eda\trafficlight1\traffic.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/07/2008 00:20:55
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
TRAFFIC
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
traffic EPM7096LC68-7 5 29 0 67 22 69 %
User Pins: 5 29 0
Project Information e:\shiyan\eda\trafficlight1\traffic.rpt
** PROJECT COMPILATION MESSAGES **
Warning: GLOBAL primitive on node 'clk' feeds logic -- non-global signal usage may result
Project Information e:\shiyan\eda\trafficlight1\traffic.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\shiyan\eda\trafficlight1\traffic.rpt
** FILE HIERARCHY **
|lpm_add_sub:98|
|lpm_add_sub:98|addcore:adder|
|lpm_add_sub:98|altshift:result_ext_latency_ffs|
|lpm_add_sub:98|altshift:carry_ext_latency_ffs|
|lpm_add_sub:98|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\shiyan\eda\trafficlight1\traffic.rpt
traffic
***** Logic for device 'traffic' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R
E E E E
S S S S V
E E E E C E E V E E
R R R R C W W C W W
V V G V V I G G G c G _ _ C _ _
s E E N E E N N N N l N M R I L M
n D D D D D T D D D k D 2 1 O 0 1
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
ew | 10 60 | EW_P0
VCCIO | 11 59 | EW_M0
en | 12 58 | GND
start | 13 57 | EW_L1
RESERVED | 14 56 | EW_R2
RESERVED | 15 55 | EW_P1
GND | 16 54 | EW_L2
RESERVED | 17 53 | VCCIO
RESERVED | 18 EPM7096LC68-7 52 | RESERVED
t11 | 19 51 | EW_R0
RESERVED | 20 50 | SN_R0
VCCIO | 21 49 | SN_P0
t15 | 22 48 | GND
t16 | 23 47 | SN_M2
RESERVED | 24 46 | SN_L0
RESERVED | 25 45 | RESERVED
GND | 26 44 | SN_M1
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
R R S S V S t G V t t G t S S S V
E E N N C N 1 N C 1 1 N 1 N N N C
S S _ _ C _ 0 D C 4 2 D 3 _ _ _ C
E E P M I L I R R L I
R R 1 0 O 2 N 1 2 1 O
V V T
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\shiyan\eda\trafficlight1\traffic.rpt
traffic
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 4/ 8( 50%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 3/16( 18%) 3/ 8( 37%) 0/16( 0%) 7/36( 19%)
C: LC33 - LC48 16/16(100%) 4/ 8( 50%) 14/16( 87%) 15/36( 41%)
D: LC49 - LC64 16/16(100%) 7/ 8( 87%) 9/16( 56%) 23/36( 63%)
E: LC65 - LC80 16/16(100%) 7/ 8( 87%) 13/16( 81%) 27/36( 75%)
F: LC81 - LC96 16/16(100%) 8/ 8(100%) 13/16( 81%) 26/36( 72%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 33/48 ( 68%)
Total logic cells used: 67/96 ( 69%)
Total shareable expanders used: 22/96 ( 22%)
Total Turbo logic cells used: 67/96 ( 69%)
Total shareable expanders not available (n/a): 27/96 ( 28%)
Average fan-in: 9.26
Total fan-in: 621
Total input pins required: 5
Total output pins required: 29
Total bidirectional pins required: 0
Total logic cells required: 67
Total flipflops required: 13
Total product terms required: 274
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 21
Synthesized logic cells: 30/ 96 ( 31%)
Device-Specific Information: e:\shiyan\eda\trafficlight1\traffic.rpt
traffic
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
67 - - INPUT G 0 0 0 0 0 4 2 clk
12 (4) (A) INPUT 0 0 0 0 0 18 26 en
10 (6) (A) INPUT 0 0 0 0 0 11 26 ew
9 (8) (A) INPUT 0 0 0 0 0 11 26 sn
13 (1) (A) INPUT 0 0 0 0 0 18 32 start
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\shiyan\eda\trafficlight1\traffic.rpt
traffic
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
62 92 F OUTPUT t 1 0 1 5 11 0 0 EW_L0
57 84 F OUTPUT t 0 0 0 0 11 0 0 EW_L1
54 77 E OUTPUT t 1 0 1 4 10 0 0 EW_L2
59 86 F OUTPUT t 0 0 0 0 11 0 0 EW_M0
61 89 F OUTPUT t 0 0 0 0 10 0 0 EW_M1
65 96 F OUTPUT t 0 0 0 0 10 0 0 EW_M2
60 88 F OUTPUT t 1 0 1 4 13 0 0 EW_P0
55 80 E OUTPUT t 1 0 1 4 3 0 0 EW_P1
51 73 E OUTPUT t 0 0 0 1 9 0 0 EW_R0
64 94 F OUTPUT t 0 0 0 0 10 0 0 EW_R1
56 81 F OUTPUT t 1 0 1 4 11 0 0 EW_R2
46 65 E OUTPUT t 1 0 1 4 13 0 0 SN_L0
42 59 D OUTPUT t 1 0 1 4 6 0 0 SN_L1
32 35 C OUTPUT t 1 0 1 4 4 0 0 SN_L2
30 37 C OUTPUT t 0 0 0 0 5 0 0 SN_M0
44 61 D OUTPUT t 0 0 0 0 11 0 0 SN_M1
47 67 E OUTPUT t 0 0 0 0 11 0 0 SN_M2
49 69 E OUTPUT t 1 0 1 5 11 0 0 SN_P0
29 40 C OUTPUT t 1 0 1 4 3 0 0 SN_P1
50 72 E OUTPUT t 1 0 1 1 10 0 0 SN_R0
40 56 D OUTPUT t 0 0 0 0 11 0 0 SN_R1
41 57 D OUTPUT t 1 0 1 4 10 0 0 SN_R2
33 33 C FF + t 0 0 0 2 0 21 16 t10 (:71)
19 24 B FF + t 0 0 0 2 1 20 16 t11 (:70)
37 51 D FF + t 0 0 0 2 2 19 16 t12 (:69)
39 53 D FF + t 0 0 0 2 3 18 16 t13 (:68)
36 49 D FF + t 0 0 0 2 4 17 16 t14 (:67)
22 19 B FF + t 0 0 0 2 2 18 16 t15 (:66)
23 17 B FF + t 0 0 0 2 2 18 15 t16 (:65)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\shiyan\eda\trafficlight1\traffic.rpt
traffic
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 54 D SOFT t 0 0 0 0 6 1 0 |LPM_ADD_SUB:98|addcore:adder|result_node5
(45) 64 D SOFT t 0 0 0 0 7 1 0 |LPM_ADD_SUB:98|addcore:adder|result_node6
- 83 F TFFE + t 0 0 0 1 10 5 14 SS02 (:46)
- 90 F TFFE + t 0 0 0 1 10 4 13 SS01 (:47)
- 93 F TFFE + t 6 0 0 1 10 3 12 SS00 (:48)
- 58 D TFFE + t 0 0 0 1 10 6 18 SS12 (:60)
- 66 E TFFE + t 0 0 0 1 10 4 15 SS11 (:61)
- 52 D TFFE + t 6 0 0 1 10 4 16 SS10 (:62)
- 87 F SOFT s t 1 0 0 4 3 1 0 ~1423~1
- 85 F SOFT s t 1 0 1 4 3 1 0 ~1432~1
- 95 F SOFT s t 0 0 0 4 3 1 0 ~1441~1
- 91 F SOFT s t 1 0 1 4 3 1 0 ~1477~1
(52) 75 E SOFT s t 2 1 1 4 3 1 0 ~1504~1
- 62 D SOFT s t 0 0 0 0 7 6 1 ~1671~1
- 71 E SOFT s t 0 0 0 4 2 1 0 ~1702~1
- 60 D SOFT s t 0 0 0 0 7 10 0 ~1946~1
- 74 E SOFT s t 0 0 0 4 3 1 0 ~1957~1
- 82 F SOFT s t 1 0 1 5 11 1 0 ~1969~1
- 79 E SOFT s t 2 0 1 4 3 1 0 ~1987~1
- 68 E SOFT s t 0 0 0 4 1 1 0 ~1993~1
- 76 E SOFT s t 2 1 1 4 3 1 0 ~1999~1
- 47 C SOFT s t 0 0 0 4 3 1 0 ~3382~1
- 38 C SOFT s t 1 1 0 4 3 1 1 ~3664~1
- 50 D SOFT s t 0 0 0 0 7 7 6 ~3669~1
- 36 C SOFT s t 2 1 1 4 3 1 1 ~3673~1
- 42 C SOFT s t 0 0 0 4 3 1 1 ~3679~1
(25) 45 C SOFT s t 0 0 0 4 1 1 0 ~3700~1
(28) 41 C SOFT s t 2 1 1 4 3 1 1 ~3703~1
(24) 48 C SOFT s t 1 0 1 4 3 1 0 ~3709~1
- 46 C SOFT s t 0 0 0 4 2 1 0 ~3718~1
- 44 C SOFT s t 0 0 0 4 2 1 1 ~3721~1
- 70 E SOFT s t 2 1 1 4 12 1 0 ~3883~1
- 55 D SOFT s t 0 0 0 0 7 10 0 ~3887~1
- 34 C SOFT s t 4 2 1 4 5 1 0 ~3892~1
- 39 C SOFT s t 1 0 1 4 5 1 0 ~3898~1
(27) 43 C SOFT s t 4 2 1 4 5 1 0 ~3922~1
- 63 D SOFT s t 1 0 1 4 11 1 0 ~3940~1
- 78 E SOFT s t 1 0 1 5 11 1 0 ~3946~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\shiyan\eda\trafficlight1\traffic.rpt
traffic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC24 t11
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