sngks32c.h

44b0 vxwork5.5 bsp 支持基于flash 39VF3201的tffs驱动

/* sngks32c.h - header for Samsung ks32c with ARM7 core */

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,12apr01,m_h  created from snds100 template.
*/

#ifndef __INCsngks32ch
#define __INCsngks32ch

#ifdef __cplusplus
extern "C" {
#endif

/*************************************************************************
* KS32C50100 SPECIAL REGISTERS 
*
*/

#define S3C44B0X_REG_BASE				0x01c00000
#define ASIC_BASE 						S3C44B0X_REG_BASE

/* System config (register bases and caching)
 */
#define S3C44B0X_SYSCFG                	(S3C44B0X_REG_BASE + 0x0000)

#define S3C44B0X_SYSCFG_CM_MASK        	0x00000006
#define S3C44B0X_SYSCFG_CM_8R_0C       	0x00000000
#define S3C44B0X_SYSCFG_CM_4R_4C       	0x00000002
#define S3C44B0X_SYSCFG_CM_0R_8C       	0x00000006
#define S3C44B0X_SYSCFG_WE             	0x00000008
#define S3C44B0X_SYSCFG_SE             	0x00000001

#define S3C44B0X_PLLCON					(S3C44B0X_REG_BASE + 0x180000)
#define S3C44B0X_CLKCON                	(S3C44B0X_REG_BASE + 0x180004)
#define S3C44B0X_LOCKTIME               (S3C44B0X_REG_BASE + 0x18000c)

/*-----------------------------------------------------------------------------
 * Watchdog
 */

#define S3C44B0X_WATCHDOG				(S3C44B0X_REG_BASE + 0x130000)

/*-----------------------------------------------------------------------------
 * Bank locations and timing
 */

#define S3C44B0X_BWSCON		           	(S3C44B0X_REG_BASE + 0x80000)
#define S3C44B0X_BANKCON0              	(S3C44B0X_REG_BASE + 0x80004)
#define S3C44B0X_BANKCON1              	(S3C44B0X_REG_BASE + 0x80008)
#define S3C44B0X_DRAMCON2              	(S3C44B0X_REG_BASE + 0x8000c)
#define S3C44B0X_DRAMCON3              	(S3C44B0X_REG_BASE + 0x80010)
#define S3C44B0X_DRAMCON4              	(S3C44B0X_REG_BASE + 0x80014)
#define S3C44B0X_DRAMCON5              	(S3C44B0X_REG_BASE + 0x80018)
#define S3C44B0X_DRAMCON6              	(S3C44B0X_REG_BASE + 0x8001c)
#define S3C44B0X_DRAMCON7              	(S3C44B0X_REG_BASE + 0x80020)
#define S3C44B0X_REFRESH               	(S3C44B0X_REG_BASE + 0x80024)
#define S3C44B0X_BANDSIZE              	(S3C44B0X_REG_BASE + 0x80028)
#define S3C44B0X_MRSRB6                	(S3C44B0X_REG_BASE + 0x8002c)
#define S3C44B0X_MRSRB7          		(S3C44B0X_REG_BASE + 0x80030)

#define S3C44B0X_BANKCON0_Tacs			0x0	/* 0clk */
#define S3C44B0X_BANKCON0_Tcos			0x0	/* 0clk */
#define S3C44B0X_BANKCON0_Tacc			0x6	/* 10clk */
#define S3C44B0X_BANKCON0_Tcoh			0x0	/* 0clk */
#define S3C44B0X_BANKCON0_Tah			0x0	/* 0clk */
#define S3C44B0X_BANKCON0_Tacp			0x0	/* 0clk */
#define S3C44B0X_BANKCON0_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON1_Tacs			0x3	/* 4clk */
#define S3C44B0X_BANKCON1_Tcos			0x3	/* 4clk */
#define S3C44B0X_BANKCON1_Tacc			0x7	/* 14clk */
#define S3C44B0X_BANKCON1_Tcoh			0x3	/* 4clk */
#define S3C44B0X_BANKCON1_Tah			0x3	/* 4clk */
#define S3C44B0X_BANKCON1_Tacp			0x3	/* 6clk */
#define S3C44B0X_BANKCON1_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON2_Tacs			0x3	/* 4clk */
#define S3C44B0X_BANKCON2_Tcos			0x3	/* 4clk */
#define S3C44B0X_BANKCON2_Tacc			0x7	/* 14clk */
#define S3C44B0X_BANKCON2_Tcoh			0x3	/* 4clk */
#define S3C44B0X_BANKCON2_Tah			0x3	/* 4clk */
#define S3C44B0X_BANKCON2_Tacp			0x3	/* 6clk */
#define S3C44B0X_BANKCON2_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON3_Tacs			0x3	/* 4clk */
#define S3C44B0X_BANKCON3_Tcos			0x3	/* 4clk */
#define S3C44B0X_BANKCON3_Tacc			0x7	/* 14clk */
#define S3C44B0X_BANKCON3_Tcoh			0x3	/* 4clk */
#define S3C44B0X_BANKCON3_Tah			0x3	/* 4clk */
#define S3C44B0X_BANKCON3_Tacp			0x3	/* 6clk */
#define S3C44B0X_BANKCON3_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON4_Tacs			0x3	/* 4clk */
#define S3C44B0X_BANKCON4_Tcos			0x3	/* 4clk */
#define S3C44B0X_BANKCON4_Tacc			0x7	/* 14clk */
#define S3C44B0X_BANKCON4_Tcoh			0x3	/* 4clk */
#define S3C44B0X_BANKCON4_Tah			0x3	/* 4clk */
#define S3C44B0X_BANKCON4_Tacp			0x3	/* 6clk */
#define S3C44B0X_BANKCON4_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON5_Tacs			0x3	/* 4clk */
#define S3C44B0X_BANKCON5_Tcos			0x3	/* 4clk */          
#define S3C44B0X_BANKCON5_Tacc			0x7	/* 14clk */        
#define S3C44B0X_BANKCON5_Tcoh			0x3	/* 4clk */          
#define S3C44B0X_BANKCON5_Tah			0x3	/* 4clk */          
#define S3C44B0X_BANKCON5_Tacp			0x3	/* 6clk */         
#define S3C44B0X_BANKCON5_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON6_Tacs			0x3	/* 4clk */         
#define S3C44B0X_BANKCON6_Tcos			0x3	/* 4clk */         
#define S3C44B0X_BANKCON6_Tacc			0x7	/* 14clk */        
#define S3C44B0X_BANKCON6_Tcoh			0x3	/* 4clk */         
#define S3C44B0X_BANKCON6_Tah			0x3	/* 4clk */         
#define S3C44B0X_BANKCON6_Tacp			0x3	/* 6clk */         
#define S3C44B0X_BANKCON6_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON7_Tacs			0x3	/* 4clk */         
#define S3C44B0X_BANKCON7_Tcos			0x3	/* 4clk */         
#define S3C44B0X_BANKCON7_Tacc			0x7	/* 14clk */        
#define S3C44B0X_BANKCON7_Tcoh			0x3	/* 4clk */         
#define S3C44B0X_BANKCON7_Tah			0x3	/* 4clk */         
#define S3C44B0X_BANKCON7_Tacp			0x3	/* 6clk */         
#define S3C44B0X_BANKCON7_PMC			0x0	/* normal(1data) */

#define S3C44B0X_BANKCON6_MT			0x3	/* SDRAM */
#define S3C44B0X_BANKCON6_Trcd			0x0	/* 2clk */
#define S3C44B0X_BANKCON6_SCAN			0x0	/* 8bit */

#define S3C44B0X_BANKCON7_MT			0x3	/* SDRAM */
#define S3C44B0X_BANKCON7_Trcd			0x0	/* 2clk */
#define S3C44B0X_BANKCON7_SCAN			0x0	/* 8bit */

#define S3C44B0X_REFRESH_REFEN			0x1	/* Refresh enable */
#define S3C44B0X_REFRESH_TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
#define S3C44B0X_REFRESH_Trp			0x0	/* 2clk */
#define S3C44B0X_REFRESH_Trc			0x1	/* 5clk */
#define S3C44B0X_REFRESH_Tchr			0x2	/* 3clk */
#define S3C44B0X_REFRESH_REFCNT			1050	/*period=15.6us, MCLK=64Mhz */

/*-----------------------------------------------------------------------------
 * INTC
 */
 
#define S3C44B0X_INTCON          		(S3C44B0X_REG_BASE + 0x200000)
#define S3C44B0X_INTPEND               	(S3C44B0X_REG_BASE + 0x200004)
#define S3C44B0X_INTMODE         		(S3C44B0X_REG_BASE + 0x200008)
#define S3C44B0X_INTMASK         		(S3C44B0X_REG_BASE + 0x20000c)

#define S3C44B0X_I_PSLV        			(S3C44B0X_REG_BASE + 0x200010)
#define S3C44B0X_I_PMST    				(S3C44B0X_REG_BASE + 0x200014)
#define S3C44B0X_I_CSLV  				(S3C44B0X_REG_BASE + 0x200018)
#define S3C44B0X_I_CMST 				(S3C44B0X_REG_BASE + 0x20001c)
#define S3C44B0X_I_ISPR  				(S3C44B0X_REG_BASE + 0x200020)
#define S3C44B0X_I_ISPC  				(S3C44B0X_REG_BASE + 0x200024)

#define S3C44B0X_F_ISPR  				(S3C44B0X_REG_BASE + 0x200038)
#define S3C44B0X_F_ISPC   				(S3C44B0X_REG_BASE + 0x20003C)

#define S3C44B0X_INTENB         		S3C44B0X_INTMASK
#define S3C44B0X_INTDIS         		S3C44B0X_INTMASK

#define S3C44B0X_INTMASK_GLOBAL         	(1<<26)
#define S3C44B0X_INT_DISABLE      		0x3ffffff
#define S3C44B0X_INTNUMLEVELS       	26
#define S3C44B0X_INTMASK_VAL        	0x3ffffff    
#define S3C44B0X_INTMODEIRQ         	0x00

/*-----------------------------------------------------------------------------
 * PIO
 */
 
#define S3C44B0X_PCONA					(S3C44B0X_REG_BASE + 0x120000)
#define S3C44B0X_PDATA					(S3C44B0X_REG_BASE + 0x120004)

#define S3C44B0X_PCONB					(S3C44B0X_REG_BASE + 0x120008)
#define S3C44B0X_PDATB					(S3C44B0X_REG_BASE + 0x12000c)

#define S3C44B0X_PCONC					(S3C44B0X_REG_BASE + 0x120010)
#define S3C44B0X_PDATC					(S3C44B0X_REG_BASE + 0x120014)
#define S3C44B0X_PUPC					(S3C44B0X_REG_BASE + 0x120018)

#define S3C44B0X_PCOND					(S3C44B0X_REG_BASE + 0x12001c)
#define S3C44B0X_PDATD					(S3C44B0X_REG_BASE + 0x120020)
#define S3C44B0X_PUPD					(S3C44B0X_REG_BASE + 0x120024)

#define S3C44B0X_PCONE					(S3C44B0X_REG_BASE + 0x120028)
#define S3C44B0X_PDATE					(S3C44B0X_REG_BASE + 0x12002c)
#define S3C44B0X_PUPE					(S3C44B0X_REG_BASE + 0x120030)

#define S3C44B0X_PCONF					(S3C44B0X_REG_BASE + 0x120034)
#define S3C44B0X_PDATF					(S3C44B0X_REG_BASE + 0x120038)
#define S3C44B0X_PUPF					(S3C44B0X_REG_BASE + 0x12003c)

#define S3C44B0X_PCONG					(S3C44B0X_REG_BASE + 0x120040)
#define S3C44B0X_PDATG					(S3C44B0X_REG_BASE + 0x120044)
#define S3C44B0X_PUPG					(S3C44B0X_REG_BASE + 0x120048)

#define S3C44B0X_SPUCR					(S3C44B0X_REG_BASE + 0x12004c)
#define S3C44B0X_EXTINT					(S3C44B0X_REG_BASE + 0x120050)
#define S3C44B0X_EXTINTPND				(S3C44B0X_REG_BASE + 0x120054)

/*-----------------------------------------------------------------------------
 * Timers
 */
 
#define S3C44B0X_TCFG0					(S3C44B0X_REG_BASE + 0x150000)
#define S3C44B0X_TCFG1					(S3C44B0X_REG_BASE + 0x150004)
#define S3C44B0X_TCON					(S3C44B0X_REG_BASE + 0x150008)

#define S3C44B0X_TCNTB0		            (S3C44B0X_REG_BASE + 0x15000c)
#define S3C44B0X_TCMPB0					(S3C44B0X_REG_BASE + 0x150010)
#define S3C44B0X_TCNTO0					(S3C44B0X_REG_BASE + 0x150014)

#define S3C44B0X_TCNTB1					(S3C44B0X_REG_BASE + 0x150018)
#define S3C44B0X_TCMPB1					(S3C44B0X_REG_BASE + 0x15001c)
#define S3C44B0X_TCNTO1					(S3C44B0X_REG_BASE + 0x150020)

#define S3C44B0X_TCNTB2					(S3C44B0X_REG_BASE + 0x150024)
#define S3C44B0X_TCMPB2					(S3C44B0X_REG_BASE + 0x150028)
#define S3C44B0X_TCNTO2					(S3C44B0X_REG_BASE + 0x15002c)

#define S3C44B0X_TCNTB3					(S3C44B0X_REG_BASE + 0x150030)
#define S3C44B0X_TCMPB3					(S3C44B0X_REG_BASE + 0x150034)
#define S3C44B0X_TCNTO3					(S3C44B0X_REG_BASE + 0x150038)

#define S3C44B0X_TCNTB4					(S3C44B0X_REG_BASE + 0x15003c)
#define S3C44B0X_TCMPB4					(S3C44B0X_REG_BASE + 0x150040)
#define S3C44B0X_TCNTO4					(S3C44B0X_REG_BASE + 0x150044)

#define S3C44B0X_TCNTB5					(S3C44B0X_REG_BASE + 0x150048)
#define S3C44B0X_TCNTO5					(S3C44B0X_REG_BASE + 0x15004c)

#define S3C44B0X_TCON_TIMER5_START		0x1000000
#define S3C44B0X_TCON_TIMER5_MANUAL		0x2000000
#define S3C44B0X_TCON_TIMER5_RELOAD		0x4000000

#define S3C44B0X_TCON_TIMER4_START		0x0100000
#define S3C44B0X_TCON_TIMER4_MANUAL		0x0200000
#define S3C44B0X_TCON_TIMER4_INVERTER	0x0400000
#define S3C44B0X_TCON_TIMER4_RELOAD		0x0800000

/*-----------------------------------------------------------------------------
 * UART
 */
 
#define S3C44B0X_UART0_BASE             (S3C44B0X_REG_BASE + 0x100000)
#define S3C44B0X_UART1_BASE             (S3C44B0X_REG_BASE + 0x104000)

#define S3C44B0X_UART_LCON              0x0000
#define S3C44B0X_UART_CON               0x0004
#define S3C44B0X_UART_FCON				0x0008
#define S3C44B0X_UART_MCON				0x000c
#define S3C44B0X_UART_TRSTAT           	0x0010
#define S3C44B0X_UART_ERSTAT			0x0014
#define S3C44B0X_UART_FSTAT				0x0018
#define S3C44B0X_UART_MSTAT				0x001c
#define S3C44B0X_UART_BRDIV				0x0028

#ifdef __S3C44B0X_BIG_ENDIAN
#define S3C44B0X_UART_TXH				0x0023
#define S3C44B0X_UART_RXH				0x0027
#else
#define S3C44B0X_UART_TXH				0x0020
#define S3C44B0X_UART_RXH				0x0024
#endif


#define S3C44B0X_UART_LCON_5_DBITS     	0x00
#define S3C44B0X_UART_LCON_6_DBITS     	0x01
#define S3C44B0X_UART_LCON_7_DBITS     	0x02
#define S3C44B0X_UART_LCON_8_DBITS     	0x03
#define S3C44B0X_UART_LCON_1_SBITS     	0x00
#define S3C44B0X_UART_LCON_2_SBITS     	0x04
#define S3C44B0X_UART_LCON_NO_PARITY   	0x00
#define S3C44B0X_UART_LCON_EVEN_PARITY 	0x00
#define S3C44B0X_UART_LCON_ODD_PARITY  	0x28
#define S3C44B0X_UART_LCON_1_PARITY    	0x30
#define S3C44B0X_UART_LCON_0_PARITY    	0x38
#define S3C44B0X_UART_LCON_IR          	0x40

#define S3C44B0X_UART_CON_RXM_MASK     	0x03
#define S3C44B0X_UART_CON_RXM_INT      	0x01
#define S3C44B0X_UART_CON_TXM_MASK     	0x0c
#define S3C44B0X_UART_CON_TXM_INT      	0x04
#define S3C44B0X_UART_CON_RX_ERR_INT   	0x40
#define S3C44B0X_UART_CON_TX_LEVEL		0x200
#define S3C44B0X_UART_CON_RX_LEVEL		0x100

#define S3C44B0X_UART_TRSTAT_RDR    	0x01
#define S3C44B0X_UART_TRSTAT_TXE		0x02  // tx empty


/*-----------------------------------------------------------------------------
 * Cache
 */

#define S3C44B0X_NCACHBE0				(S3C44B0X_REG_BASE + 0x4)
#define S3C44B0X_NCACHBE1				(S3C44B0X_REG_BASE + 0x8)

#define Non_Cache_Start	(0x2000000)
#define Non_Cache_End 	(0xc000000)

#define S3C44B0X_CACHE_SET0_ADDR       	0x10000000
#define S3C44B0X_CACHE_SET1_ADDR       	0x10000800
#define S3C44B0X_CACHE_SET2_ADDR       	0x10001000
#define S3C44B0X_CACHE_SET3_ADDR       	0x10001800
#define S3C44B0X_CACHE_TAG_ADDR 			0x10002000
#define S3C44B0X_CACHE_LRU_ADDR			0x10004000

#define SERIAL_A_BASE_ADR       		S3C44B0X_UART0_BASE	/* UART A base address */
#define SERIAL_B_BASE_ADR       		S3C44B0X_UART1_BASE	/* UART B base address */
#define SNGKS32C_TIMER_BASE      		0x0A800000        	/* Address of base of timer */


#ifdef __cplusplus
}
#endif

#endif /* __INCsngks32ch */