t_fifo.v

实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能

`timescale 1ns/1ns
`define clk_circul 30
//`include "/export/home/ap/lib/smic18/feview~2/version2.2/STD/Verilog/smic18.v"

module t_fifo;
reg reset,clk;
reg w_en,r_en;
reg[7:0]din;
wire dout;
wire ov;

always #`clk_circul  clk=~clk;

 
 
initial
    begin
      #0  clk=0;
           reset=0;
           din=8'b11110000;
           w_en=0;
           r_en=0;
       #20 reset=1;
            din=8'b11001100;
            w_en=1;
           r_en=0;
       #35
           w_en=0;
           r_en=1;
           
        #70 w_en=1;
           din=8'b10101110;
            r_en=0;
       #100
           w_en=0;
           r_en=1;
       #70 w_en=1;
           din=8'b0101110;
           r_en=0;
           
            
            
           
           
       #100000   $stop;
     end
     
     
     
              
initial
   begin
        #0 $shm_open("wave.shm");
         $shm_probe("AS");
         //$sdf_annotate("fifo.sdf",ff);	
           #1000 $shm_close;
           #200000 $finish;
    end
    
  fifo  ff(.clk(clk),.reset(reset),.w_en(w_en),.r_en(r_en),.din(din),.dout(dout));
   
 endmodule