smchw.h

aesop s3c2440a BSP for windowsce 6.0

// Bit  8 - NOCRC - Do insert the CRC at the end of transmitted frames automatically
// Bit  7 - PAD_EN - Do pad frames shorter than the minimum of 64 bytes automatically
// Bit  2 - FORCOL - Don't force a collision
// Bit  1 - LOOP - Don't loop back frames internally without transmitting
// Bit  0 - TXENA - Do enable transmission
#define TCR_REG_INIT 0x0081

// This value is used to initialize the Memory Configuration Register (Pg 42 of the SMC91C94 spec):
// Bits 7-0 - MEMORY RESERVED FOR TRANSMIT - Reserve memory for transmit purposes only.  I need to
//  reserve enough memory for one maximum sized Frame for transmission purposes.  This will prevent
//  deadlock conditions in which Frames keep coming in, but can't be acknowledged because of a lack of memory.
// The amount of memory reserved is calculated as MCR_REG_INIT * 256 * M, where M is 1 for the 91C94
//  (pg 42 of the SMC91C94 spec.).  So, for a 1500 byte frame, I need 1500 / 256 = 6 memory pages.
#define MCR_REG_INIT 0x0006

// This value is used to initialize the Receive Control Register (Pg 39 of the SMC91C94 spec):
// Bit 15 - SOFT RST - Don't do a soft reset
// Bit 14 - FILT_CAR - Don't filter the carrier signal
// Bit  9 - STRIP CRC - Don't strip the CRC from the Frame
// Bit  8 - RXEN - Do enable the Frame receiver
// Bit  2 - ALMUL - Don't accept all multicast frames
// Bit  1 - PRMS - Don't go into promiscuous mode
// Bit  0 - RX_ABORT - Write the receive abort flag low
//	(set by a frame that was longer than 1532 bytes or out of buffer memory error)
#define RCR_REG_INIT 0x0100








/* PHY Control Register */
#define PHY_CNTL_REG            0x00
   #define PHY_CNTL_RST            0x8000  /* 1=PHY Reset */
   #define PHY_CNTL_LPBK           0x4000  /* 1=PHY Loopback */
   #define PHY_CNTL_SPEED          0x2000  /* 1=100Mbps, 0=10Mpbs */
   #define PHY_CNTL_ANEG_EN        0x1000 /* 1=Enable Auto negotiation */
   #define PHY_CNTL_PDN            0x0800  /* 1=PHY Power Down mode */
   #define PHY_CNTL_MII_DIS        0x0400  /* 1=MII 4 bit interface disabled */
   #define PHY_CNTL_ANEG_RST       0x0200 /* 1=Reset Auto negotiate */
   #define PHY_CNTL_DPLX           0x0100  /* 1=Full Duplex, 0=Half Duplex */
   #define PHY_CNTL_COLTST         0x0080  /* 1= MII Colision Test */

/* PHY Status Register */
#define PHY_STAT_REG            0x01
   #define PHY_STAT_CAP_T4         0x8000  /* 1=100Base-T4 capable */
   #define PHY_STAT_CAP_TXF        0x4000  /* 1=100Base-X full duplex capable */
   #define PHY_STAT_CAP_TXH        0x2000  /* 1=100Base-X half duplex capable */
   #define PHY_STAT_CAP_TF         0x1000  /* 1=10Mbps full duplex capable */
   #define PHY_STAT_CAP_TH         0x0800  /* 1=10Mbps half duplex capable */
   #define PHY_STAT_CAP_SUPR       0x0040  /* 1=recv mgmt frames with not preamble */
   #define PHY_STAT_ANEG_ACK       0x0020  /* 1=ANEG has completed */
   #define PHY_STAT_REM_FLT        0x0010  /* 1=Remote Fault detected */
   #define PHY_STAT_CAP_ANEG       0x0008  /* 1=Auto negotiate capable */
   #define PHY_STAT_LINK           0x0004  /* 1=valid link */
   #define PHY_STAT_JAB            0x0002  /* 1=10Mbps jabber condition */
   #define PHY_STAT_EXREG          0x0001  /* 1=extended registers implemented */

/* PHY Identifier Registers */
#define PHY_ID1_REG             0x02    /* PHY Identifier 1 */
#define PHY_ID2_REG             0x03    /* PHY Identifier 2 */

/* PHY Auto-Negotiation Advertisement Register */
#define PHY_AD_REG              0x04
   #define PHY_AD_NP               0x8000  /* 1=PHY requests exchange of Next Page */
   #define PHY_AD_ACK              0x4000  /* 1=got link code word from remote */
   #define PHY_AD_RF               0x2000  /* 1=advertise remote fault */
   #define PHY_AD_T4               0x0200  /* 1=PHY is capable of 100Base-T4 */
   #define PHY_AD_TX_FDX           0x0100  /* 1=PHY is capable of 100Base-TX FDPLX */
   #define PHY_AD_TX_HDX           0x0080  /* 1=PHY is capable of 100Base-TX HDPLX */
   #define PHY_AD_10_FDX           0x0040  /* 1=PHY is capable of 10Base-T FDPLX */
   #define PHY_AD_10_HDX           0x0020  /* 1=PHY is capable of 10Base-T HDPLX */
   #define PHY_AD_CSMA             0x0001  /* 1=PHY is capable of 802.3 CMSA */

/* PHY Auto-negotiation Remote End Capability Register */
#define PHY_RMT_REG             0x05
/* Uses same bit definitions as PHY_AD_REG */

/* PHY Configuration Register 1 */
#define PHY_CFG1_REG            0x10
   #define PHY_CFG1_LNKDIS         0x8000  /* 1=Rx Link Detect Function disabled */
   #define PHY_CFG1_XMTDIS         0x4000  /* 1=TP Transmitter Disabled */
   #define PHY_CFG1_XMTPDN         0x2000  /* 1=TP Transmitter Powered Down */
   #define PHY_CFG1_BYPSCR         0x0400  /* 1=Bypass scrambler/descrambler */
   #define PHY_CFG1_UNSCDS         0x0200  /* 1=Unscramble Idle Reception Disable */
   #define PHY_CFG1_EQLZR          0x0100  /* 1=Rx Equalizer Disabled */
   #define PHY_CFG1_CABLE          0x0080  /* 1=STP(150ohm), 0=UTP(100ohm) */
   #define PHY_CFG1_RLVL0          0x0040  /* 1=Rx Squelch level reduced by 4.5db */
   #define PHY_CFG1_TLVL_SHIFT     2       /* Transmit Output Level Adjust */
   #define PHY_CFG1_TLVL_MASK      0x003C
   #define PHY_CFG1_TRF_MASK       0x0003  /* Transmitter Rise/Fall time */

/* PHY Configuration Register 2 */
#define PHY_CFG2_REG            0x11
   #define PHY_CFG2_APOLDIS        0x0020  /* 1=Auto Polarity Correction disabled */
   #define PHY_CFG2_JABDIS         0x0010  /* 1=Jabber disabled */
   #define PHY_CFG2_MREG           0x0008  /* 1=Multiple register access (MII mgt) */
   #define PHY_CFG2_INTMDIO        0x0004  /* 1=Interrupt signaled with MDIO pulseo */

/* PHY Status Output (and Interrupt status) Register */
#define PHY_INT_REG             0x12    /* Status Output (Interrupt Status) */
   #define PHY_INT_INT             0x8000  /* 1=bits have changed since last read */
   #define PHY_INT_LNKFAIL         0x4000  /* 1=Link Not detected */
   #define PHY_INT_LOSSSYNC        0x2000  /* 1=Descrambler has lost sync */
   #define PHY_INT_CWRD            0x1000  /* 1=Invalid 4B5B code detected on rx */
   #define PHY_INT_SSD             0x0800  /* 1=No Start Of Stream detected on rx */
   #define PHY_INT_ESD             0x0400  /* 1=No End Of Stream detected on rx */
   #define PHY_INT_RPOL            0x0200  /* 1=Reverse Polarity detected */
   #define PHY_INT_JAB             0x0100  /* 1=Jabber detected */
   #define PHY_INT_SPDDET          0x0080  /* 1=100Base-TX mode, 0=10Base-T mode */
   #define PHY_INT_DPLXDET         0x0040  /* 1=Device in Full Duplex */

/* PHY Interrupt/Status Mask Register */
#define PHY_MASK_REG            0x13    /* Interrupt Mask */
/* Uses the same bit definitions as PHY_INT_REG */





/* Transmit Control Register */
/* BANK 0  */
//#define TCR_REG         0x0000  /* transmit control register */
#define TCR_ENABLE      0x0001  /* When 1 we can transmit */
#define TCR_LOOP        0x0002  /* Controls output pin LBK */
#define TCR_FORCOL      0x0004  /* When 1 will force a collision */
#define TCR_PAD_EN      0x0080  /* When 1 will pad tx frames < 64 bytes w/0 */
#define TCR_NOCRC       0x0100  /* When 1 will not append CRC to tx frames */
#define TCR_MON_CSN     0x0400  /* When 1 tx monitors carrier */
#define TCR_FDUPLX      0x0800  /* When 1 enables full duplex operation */
#define TCR_STP_SQET    0x1000  /* When 1 stops tx if Signal Quality Error */
#define TCR_EPH_LOOP    0x2000  /* When 1 enables EPH block loopback */
#define TCR_SWFDUP      0x8000  /* When 1 enables Switched Full Duplex mode */

#define TCR_CLEAR       0       /* do NOTHING */
/* the default settings for the TCR register : */
/* QUESTION: do I want to enable padding of short packets ? */
#define TCR_DEFAULT     TCR_ENABLE


/* EPH Status Register */
/* BANK 0  */
#define EPH_STATUS_REG  0x0002
#define ES_TX_SUC       0x0001  /* Last TX was successful */
#define ES_SNGL_COL     0x0002  /* Single collision detected for last tx */
#define ES_MUL_COL      0x0004  /* Multiple collisions detected for last tx */
#define ES_LTX_MULT     0x0008  /* Last tx was a multicast */
#define ES_16COL        0x0010  /* 16 Collisions Reached */
#define ES_SQET         0x0020  /* Signal Quality Error Test */
#define ES_LTXBRD       0x0040  /* Last tx was a broadcast */
#define ES_TXDEFR       0x0080  /* Transmit Deferred */
#define ES_LATCOL       0x0200  /* Late collision detected on last tx */
#define ES_LOSTCARR     0x0400  /* Lost Carrier Sense */
#define ES_EXC_DEF      0x0800  /* Excessive Deferral */
#define ES_CTR_ROL      0x1000  /* Counter Roll Over indication */
#define ES_LINK_OK      0x4000  /* Driven by inverted value of nLNK pin */
#define ES_TXUNRN       0x8000  /* Tx Underrun */


/* Receive Control Register */
/* BANK 0  */
#define RCR_REG         0x0004
   #define RCR_RX_ABORT    0x0001  /* Set if a rx frame was aborted */
   #define RCR_PRMS        0x0002  /* Enable promiscuous mode */
   #define RCR_ALMUL       0x0004  /* When set accepts all multicast frames */
   #define RCR_RXEN        0x0100  /* IFF this is set, we can receive packets */
   #define RCR_STRIP_CRC   0x0200  /* When set strips CRC from rx packets */
   #define RCR_ABORT_ENB   0x0200  /* When set will abort rx on collision */
   #define RCR_FILT_CAR    0x0400  /* When set filters leading 12 bit s of carrier */
   #define RCR_SOFTRST     0x8000  /* resets the chip */

/* the normal settings for the RCR register : */
#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
#define RCR_CLEAR       0x0     /* set it to a base state */

/* Counter Register */
/* BANK 0  */
//#define COUNTER_REG     0x0006

/* Memory Information Register */
/* BANK 0  */
//#define MIR_REG         0x0008

/* Receive/Phy Control Register */
/* BANK 0  */
#define RPC_REG         0x000A
   #define RPC_SPEED       0x2000  /* When 1 PHY is in 100Mbps mode. */
   #define RPC_DPLX        0x1000  /* When 1 PHY is in Full-Duplex Mode */
   #define RPC_ANEG        0x0800  /* When 1 PHY is in Auto-Negotiate Mode */
   #define RPC_LSXA_SHFT   5       /* Bits to shift LS2A,LS1A,LS0A to lsb */
   #define RPC_LSXB_SHFT   2       /* Bits to get LS2B,LS1B,LS0B to lsb */
      #define RPC_LED_100_10  (0x00)  /* LED = 100Mbps OR's with 10Mbps link detect */
      #define RPC_LED_RES     (0x01)  /* LED = Reserved */
      #define RPC_LED_10      (0x02)  /* LED = 10Mbps link detect */
      #define RPC_LED_FD      (0x03)  /* LED = Full Duplex Mode */
      #define RPC_LED_TX_RX   (0x04)  /* LED = TX or RX packet occurred */
      #define RPC_LED_100     (0x05)  /* LED = 100Mbps link dectect */
      #define RPC_LED_TX      (0x06)  /* LED = TX packet occurred */
      #define RPC_LED_RX      (0x07)  /* LED = RX packet occurred */

/* SMSC reference design: LEDa --> green, LEDb --> yellow */
#define RPC_DEFAULT     ( RPC_SPEED | RPC_DPLX | RPC_ANEG       \
                        | (RPC_LED_100_10 << RPC_LSXA_SHFT)     \
                        | (RPC_LED_TX_RX << RPC_LSXB_SHFT)      )


/* Bank 0 0x000C is reserved */

/* Bank Select Register */
/* All Banks */
#define BSR_REG 0x000E






/* Multicast Table Registers */
/* BANK 3 */
#define MCAST_REG1      0x0000
#define MCAST_REG2      0x0002
#define MCAST_REG3      0x0004
#define MCAST_REG4      0x0006


/* Management Interface Register (MII) */
/* BANK 3 */
#define MII_REG         0x0008
#define MII_MSK_CRS100  0x4000 /* Disables CRS100 detection during tx half dup */
#define MII_MDOE        0x0008 /* MII Output Enable */
#define MII_MCLK        0x0004 /* MII Clock, pin MDCLK */
#define MII_MDI         0x0002 /* MII Input, pin MDI */
#define MII_MDO         0x0001 /* MII Output, pin MDO */


/* Revision Register */
/* BANK 3 */
#define REV_REG         0x000A /* ( hi: chip id   low: rev # ) */


/* Early RCV Register */
/* BANK 3 */
/* this is NOT on SMC9192 */
//#define ERCV_REG        0x000C
#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
#define ERCV_THRESHOLD  0x001F /* ERCV Threshold Mask */



#endif  // _SMCHW_H