smchw.h

aesop s3c2440a BSP for windowsce 6.0

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  
    smchw.h
Abstract:  
    Definitions for the SMC9000 registers

Notes: 

--*/
#ifndef _SMCHW_H
#define _SMCHW_H


// These registers are in Bank 0 at the given offsets from the base address
// Since they are set up for 32-bit accesses, the offsets are multiplied by 2 from
//  the numbers given in the SMC91C94 spec.
#define TCR_REG			0
#define EPHSTATUS_REG	2
#define COUNTER_REG		6
#define MIR_REG			8
#define MCR_REG			10
// The register at offset 24 is reserved
// The bank select register is the same for all 4 banks
#define BANKSEL_REG		14


// Bank 1 registers
/* Configuration Reg */
#define CONFIG_REG      0x0000
#define CONFIG_EXT_PHY  0x0200  /* 1=external MII, 0=internal Phy */
#define CONFIG_GPCNTRL  0x0400  /* Inverse value drives pin nCNTRL */
#define CONFIG_NO_WAIT  0x1000  /* When 1 no extra wait states on ISA bus */

#define BASE_REG           0x0002
#define MACADDR0_REG       0x0004
#define MACADDR1_REG       0x0006
#define MACADDR2_REG       0x0008
#define GENERAL_REG	   0x000A

/* Control Register */
#define CONTROL_REG	   0x000C
   #define CTL_RCV_BAD     0x4000 /* When 1 bad CRC packets are received */
   #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
   #define CTL_LE_ENABLE   0x0080 /* When 1 enables Link Error interrupt */
   #define CTL_CR_ENABLE   0x0040 /* When 1 enables Counter Rollover interrupt */
   #define CTL_TE_ENABLE   0x0020 /* When 1 enables Transmit Error interrupt */
   #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
   #define CTL_RELOAD      0x0002 /* When set reads EEPROM into registers */
   #define CTL_STORE       0x0001 /* When set stores registers into EEPROM */

#define CTL_DEFAULT     (CTL_AUTO_RELEASE) /* Autorelease enabled*/




//--------------------------------------------------------------------------------
// Bank 2 _REGisters
//--------------------------------------------------------------------------------
/* MMU Command Register */
#define MMU_CMD_REG     0x0000
#define MC_BUSY         1       /* When 1 the last release has not completed */
#define MC_NOP          (0<<5)  /* No Op */
#define MC_ALLOC        (1<<5)  /* OR with number of 256 byte packets */
#define MC_RESET        (2<<5)  /* Reset MMU to initial state */
#define MC_REMOVE       (3<<5)  /* Remove the current rx packet */
#define MC_RELEASE      (4<<5)  /* Remove and release the current rx packet */
#define MC_FREEPKT      (5<<5)  /* Release packet in PNR register */
#define MC_ENQUEUE      (6<<5)  /* Enqueue the packet for transmit */
#define MC_RSTTXFIFO    (7<<5)  /* Reset the TX FIFOs */

/* Packet Number Register */
#define PN_REG          0x0002

/* Allocation Result Register */
#define AR_REG          0x0003
#define AR_FAILED       0x80    /* Alocation Failed */

/* RX FIFO Ports Register */
#define RXFIFO_REG      0x0004  /* Must be read as a word */
#define RXFIFO_REMPTY   0x8000  /* RX FIFO Empty */

/* TX FIFO Ports Register */
#define TXFIFO_REG      RXFIFO_REG      /* Must be read as a word */
#define TXFIFO_TEMPTY   0x80    /* TX FIFO Empty */

/* Pointer Register */
#define PTR_REG         0x0006
#define PTR_RCV         0x8000 /* 1=Receive area, 0=Transmit area */
#define PTR_AUTOINC     0x4000 /* Auto increment the pointer on each access */
#define PTR_READ        0x2000 /* When 1 the operation is a read */
#define PTR_NOTEMPTY    0x0800 /* When 1 _do not_ write fifo DATA REG */

/* Data Register */
#define DATA_REG       0x0008
   #define RS_ALGNERR      0x8000
   #define RS_BRODCAST     0x4000
   #define RS_BADCRC       0x2000
   #define RS_ODDFRAME     0x1000  /* bug: the LAN91C111 never sets this on receive */
   #define RS_TOOLONG      0x0800
   #define RS_TOOSHORT     0x0400
   #define RS_MULTICAST    0x0001
   #define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)

/* Interrupt Status/Acknowledge Register */
#define SMC91111_INT_REG        0x000C

/* Interrupt Mask Register */
#define IM_REG          0x000D
#define IM_MDINT        0x80 /* PHY MI Register 18 Interrupt */
#define IM_ERCV_INT     0x40 /* Early Receive Interrupt */
#define IM_EPH_INT      0x20 /* Set by Etheret Protocol Handler section */
#define IM_RX_OVRN_INT  0x10 /* Set by Receiver Overruns */
#define IM_ALLOC_INT    0x08 /* Set when allocation request is completed */
#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
#define IM_TX_INT       0x02 /* Transmit Interrrupt */
#define IM_RCV_INT      0x01 /* Receive Interrupt */



/* External Register */
/* BANK 7 */
#define EXT_REG         0x0000




// Bank 3 registers
#define MULTITAB_REG0	0
#define MULTITAB_REG1	2
#define MULTITAB_REG2	4
#define MULTITAB_REG3	6
#define MGMT_REG		8
#define REVISION_REG	10
#define ERCV_REG		12

// These values are written to the bank select register to change banks.
#define BANK0 0x3300
#define BANK1 0x3301
#define BANK2 0x3302
#define BANK3 0x3303

// Config reg defs
#define CFG_NO_WAIT             0x1000  //  No wait states
#define CFG_GPCNTRL             0x0400  
#define CFG_EXTPHY              0x0200  
#define CFG_EPH_POWER_EN        0x8000





// EPH Status reg (also used for TX status word)
#define EPH_UNDERRUN            0x8000  //  Frame uderrun
#define EPH_LINKERROR           0x4000  //  10BASET link error condition
#define EPH_RXOVERRUN           0x2000  //  Receiver overrun
#define EPH_COUNTER             0x1000  //  Counter roll over
#define EPH_EXDEFER             0x0800  //  Excessive deferral
#define EPH_CARRIER             0x0400  //  Carrier not present
#define EPH_LATE                0x0200  //  Late collision
#define EPH_DEFER               0x0080  //  Frame was deferred
#define EPH_BCAST               0x0040  //  Last frame was broadcast
#define EPH_SQET                0x0020  //  Signal Quality Error
#define EPH_16COL               0x0010  //  Too many collisions
#define EPH_MCAST               0x0008  //  Last frame was multicast
#define EPH_MULTICOL            0x0004  //  Multiple collisions on last frame
#define EPH_1COL                0x0002  //  Single collision on last frame
#define EPH_TX_OK               0x0001  //  Frame successfully transmitted


// MMU Commands
#define CMD_NOP                 0       //  No-Op command
#define CMD_ALLOC               0x0020  //  Allocate memory
#define CMD_RESET               0x0040  //  Reset MMU to initial state
#define CMD_REM_TOP             0x0060  //  Remove frame from top of RX fifo
#define CMD_REM_REL_TOP         0x0080  //  Remove and release top of RX fifo
#define CMD_REL_SPEC            0x00a0  //  Release specific packet
#define CMD_ENQ_TX              0x00c0  //  Enqueue to xmit fifo
#define CMD_ENQ_RX              0x00e0  //  Reset xmit fifos (should only be done
                                        //  with transmitter disabled)
#define MMU_CMD_BUSY            0x0001  //  MMU busy, don't modify PNR

// Allocation Result Register (low byte of PNR_ARR_REG)
#define ARR_FAIL                0x80    //  Allocation failed
#define ARR_ALLOC_MSK           0x7f    //  Mask allocated packet number
                                        //  Actually 1fh but use full mask for
                                        //  upward compatibility.

// Pointer Register (POINTER_REG)
#define PTR_RCV                 0x8000  //  Access is to receive area
#define PTR_AUTO                0x4000  //  Auto-increment on access
#define PTR_READ                0x2000  //  =1 then read operation
                                        //  =0 then write operation
#define PTR_ETEN                0x1000  //  Detect early transmit underrun
#define PTR_NOT_EMPTY           0x0800  //  Write fifo not empty
#define PTR_OFFSET              0x03ff  //  Mask pointer value

// Fifo Ports Register (FIFOPORTS_REG)
#define FIFO_EMPTY              0x80    //  No packet at top of fifo
#define FIFO_TX_PKT_MASK        0x7f    //  Mask top packet number
                                        //  Actually 1fh but use full mask for
                                        //  upward compatibility.

// Interrupt flags that can be set/acknowledged
#define ERCV_INT	0x0040
#define EPH_INT		0x0020
#define RX_OVRN_INT	0x0010
#define ALLOC_INT	0x0008
#define TXEMPTY_INT	0x0004
#define TX_INT		0x0002
#define RCV_INT		0x0001

// Interrupt mask bits, if these are set the interrupt is enabled
#define ERCV_INTM		0x4000
#define EPH_INTM		0x2000
#define RX_OVRN_INTM	0x1000
#define ALLOC_INTM		0x0800
#define TXEMPTY_INTM	0x0400
#define TX_INTM			0x0200
#define RCV_INTM		0x0100

// This value is used to intialize the Control Register (Pg 49 of the SMC91C94 spec):
// Bit 14 - RCV_BAD - Don't receive Frames with bad CRC
// Bit 13 - PWRDN - Don't go into power down mode
// Bit 11 - AUTO RELEASE - Do use the auto memory release feature for successfully transmitted Frames
// Bit  7 - LE ENABLE - Don't generate interrupts for link errors (merged through EPH_INT)
// Bit  6 - CR ENABLE - Don't generate interrupts for counter roll over (merged through EPH_INT)
// Bit  5 - TE ENABLE - Do generate interrupts for transmit errors (merged through EPH_INT)
// Bit  2 - EEPROM SELECT - Don't select the EEPROM
// Bit  1 - RELOAD - Don't reload EEPROM data
// Bit  0 - STORE - Don't store EEPROM data
#define CONTROL_REG_INIT 0x0920

// This value is used to intialize the Transmit Control Register (Pg 35 of the SMC91C94 spec):
// Bit 13 - EPH LOOP - Don't do EPH Internal Loopback
// Bit 12 - STP SQET - Don't stop transmission on SQET error
// DANGER - May need FDUPLX for IPX
// Bit 11 - FDUPLX - Don't use full duplex operation so that Frames sourced by this card are not received by it
// Bit 10 - MON_CSN - Don't monitor carrier while transmitting.  Transmission will continue whether the card senses
//  it's own carrier after the preamble or not.