📄 cim_regs.h
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typedef struct tagPLLFrequency
{
unsigned long pll_value;
unsigned long frequency;
} PLL_FREQUENCY;
/* VG MSRS */
#define DC3_SPARE_MSR 0x2011
#define DC3_RAM_CTL 0x2012
/* DC3_SPARE_MSR DEFINITIONS */
#define DC3_SPARE_DISABLE_CFIFO_HGO 0x00000800
#define DC3_SPARE_VFIFO_ARB_SELECT 0x00000400
#define DC3_SPARE_WM_LPEN_OVRD 0x00000200
#define DC3_SPARE_LOAD_WM_LPEN_MASK 0x00000100
#define DC3_SPARE_DISABLE_INIT_VID_PRI 0x00000080
#define DC3_SPARE_DISABLE_VFIFO_WM 0x00000040
#define DC3_SPARE_DISABLE_CWD_CHECK 0x00000020
#define DC3_SPARE_PIX8_PAN_FIX 0x00000010
#define DC3_SPARE_FIRST_REQ_MASK 0x00000002
/* VG DIAG DEFINITIONS */
#define DC3_MBD_DIAG_EN0 0x00008000
#define DC3_MBD_DIAG_EN1 0x80000000
#define DC3_DIAG_DOT_CRTC_DP 0x00000082
#define DC3_DIAG_DOT_CRTC_DP_HIGH 0x00820000
#define DC3_DIAG_EVEN_FIELD 0x00002000
/*----------------------------------------------------------------*/
/* DISPLAY FILTER DEFINITIONS */
/*----------------------------------------------------------------*/
#define DF_VIDEO_CONFIG 0x00000000
#define DF_DISPLAY_CONFIG 0x00000008
#define DF_VIDEO_X_POS 0x00000010
#define DF_VIDEO_Y_POS 0x00000018
#define DF_VIDEO_SCALER 0x00000020
#define DF_VIDEO_COLOR_KEY 0x00000028
#define DF_VIDEO_COLOR_MASK 0x00000030
#define DF_PALETTE_ADDRESS 0x00000038
#define DF_PALETTE_DATA 0x00000040
#define DF_SATURATION_LIMIT 0x00000048
#define DF_VID_MISC 0x00000050
#define DF_VIDEO_YSCALE 0x00000060
#define DF_VIDEO_XSCALE 0x00000068
#define DF_VID_CRC 0x00000088
#define DF_VID_CRC32 0x00000090
#define DF_VID_ALPHA_CONTROL 0x00000098
#define DF_CURSOR_COLOR_KEY 0x000000A0
#define DF_CURSOR_COLOR_MASK 0x000000A8
#define DF_CURSOR_COLOR_1 0x000000B0
#define DF_CURSOR_COLOR_2 0x000000B8
#define DF_ALPHA_XPOS_1 0x000000C0
#define DF_ALPHA_YPOS_1 0x000000C8
#define DF_ALPHA_COLOR_1 0x000000D0
#define DF_ALPHA_CONTROL_1 0x000000D8
#define DF_ALPHA_XPOS_2 0x000000E0
#define DF_ALPHA_YPOS_2 0x000000E8
#define DF_ALPHA_COLOR_2 0x000000F0
#define DF_ALPHA_CONTROL_2 0x000000F8
#define DF_ALPHA_XPOS_3 0x00000100
#define DF_ALPHA_YPOS_3 0x00000108
#define DF_ALPHA_COLOR_3 0x00000110
#define DF_ALPHA_CONTROL_3 0x00000118
#define DF_VIDEO_REQUEST 0x00000120
#define DF_ALPHA_WATCH 0x00000128
#define DF_VIDEO_TEST_MODE 0x00000130
#define DF_VID_YPOS_EVEN 0x00000138
#define DF_VID_ALPHA_Y_EVEN_1 0x00000140
#define DF_VID_ALPHA_Y_EVEN_2 0x00000148
#define DF_VID_ALPHA_Y_EVEN_3 0x00000150
#define DF_VIDEO_PANEL_TIM1 0x00000400
#define DF_VIDEO_PANEL_TIM2 0x00000408
#define DF_POWER_MANAGEMENT 0x00000410
#define DF_DITHER_CONTROL 0x00000418
#define DF_DITHER_ACCESS 0x00000448
#define DF_DITHER_DATA 0x00000450
#define DF_PANEL_CRC 0x00000458
#define DF_PANEL_CRC32 0x00000468
#define DF_COEFFICIENT_BASE 0x00001000
/* DF_VIDEO_CONFIG BIT DEFINITIONS */
#define DF_VCFG_VID_EN 0x00000001
#define DF_VCFG_VID_INP_FORMAT 0x0000000C
#define DF_VCFG_SC_BYP 0x00000020
#define DF_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00
#define DF_VCFG_INIT_READ_MASK 0x01FF0000
#define DF_VCFG_LINE_SIZE_BIT8 0x08000000
#define DF_VCFG_LINE_SIZE_BIT9 0x04000000
#define DF_VCFG_4_2_0_MODE 0x10000000
#define DF_VCFG_UYVY_FORMAT 0x00000000
#define DF_VCFG_Y2YU_FORMAT 0x00000004
#define DF_VCFG_YUYV_FORMAT 0x00000008
#define DF_VCFG_YVYU_FORMAT 0x0000000C
/* DF_DISPLAY_CONFIG BIT DEFINITIONS */
#define DF_DCFG_DIS_EN 0x00000001
#define DF_DCFG_HSYNC_EN 0x00000002
#define DF_DCFG_VSYNC_EN 0x00000004
#define DF_DCFG_DAC_BL_EN 0x00000008
#define DF_DCFG_CRT_HSYNC_POL 0x00000100
#define DF_DCFG_CRT_VSYNC_POL 0x00000200
#define DF_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
#define DF_DCFG_CRT_SYNC_SKW_INIT 0x00010000
#define DF_DCFG_PWR_SEQ_DLY_MASK 0x000E0000
#define DF_DCFG_PWR_SEQ_DLY_INIT 0x00080000
#define DF_DCFG_VG_CK 0x00100000
#define DF_DCFG_GV_PAL_BYP 0x00200000
#define DF_DAC_VREF 0x04000000
/* DF_VID_MISC BIT DEFINITIONS */
#define DF_GAMMA_BYPASS_BOTH 0x00000001
#define DF_DAC_POWER_DOWN 0x00000400
#define DF_ANALOG_POWER_DOWN 0x00000800
#define DF_USER_IMPLICIT_SCALING 0x00001000
/* DF_VID_ALPHA_CONTROL DEFINITIONS */
#define DF_HD_VIDEO 0x00000040
#define DF_YUV_CSC_EN 0x00000080
#define DF_NO_CK_OUTSIDE_ALPHA 0x00000100
#define DF_HD_GRAPHICS 0x00000200
#define DF_CSC_VIDEO_YUV_TO_RGB 0x00000400
#define DF_CSC_GRAPHICS_RGB_TO_YUV 0x00000800
#define DF_CSC_VOP_RGB_TO_YUV 0x00001000
#define DF_VIDEO_INPUT_IS_RGB 0x00002000
#define DF_VID_ALPHA_EN 0x00004000
#define DF_ALPHA_DRGB 0x00008000
/* VIDEO CURSOR COLOR KEY DEFINITIONS */
#define DF_CURSOR_COLOR_KEY_ENABLE 0x20000000
/* ALPHA COLOR BIT DEFINITION */
#define DF_ALPHA_COLOR_ENABLE 0x01000000
/* ALPHA CONTROL BIT DEFINITIONS */
#define DF_ACTRL_WIN_ENABLE 0x00010000
#define DF_ACTRL_LOAD_ALPHA 0x00020000
#define DF_ACTRL_PERPIXEL_EN 0x00040000
/* DF_VIDEO_SCALER DEFINITIONS */
#define DF_SCALE_128_PHASES 0x00002000
#define DF_SCALE_DOUBLE_H_DOWNSCALE 0x00004000
/* DEFAULT PANEL TIMINGS DEFINITIONS */
#define DF_DEFAULT_TFT_PMTIM1 0x00000000
#define DF_DEFAULT_XVGA_PMTIM1 0x00000000
#define DF_DEFAULT_TFT_PMTIM2 0x08C00000
#define DF_DEFAULT_XVGA_PMTIM2 0x08C10000
#define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF
#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F
#define DF_DEFAULT_XVGA_PAD_SEL_LOW 0x00000000
#define DF_DEFAULT_XVGA_PAD_SEL_HIGH 0x00000000
#define DF_DEFAULT_DITHCTL 0x00000070
#define DF_DEFAULT_TV_PAD_SEL_HIGH 0x000000BF
#define DF_DEFAULT_TV_PAD_SEL_LOW 0xDFFFFFFF
#define DF_INVERT_VOP_CLOCK 0x00000080
/* DF_VIDEO_PANEL_TIM2 DEFINITIONS */
#define DF_PMTIM2_TFT_PASSHTHROUGH 0x40000000
/* DF_POWER_MANAGEMENT DEFINITIONS */
#define DF_PM_PANEL_ON 0x01000000
#define DF_PM_INVERT_SHFCLK 0x00002000
/* DISPLAY FILTER MSRS */
#define DF_MBD_MSR_DIAG_DF 0x2010
#define DF_MSR_PAD_SEL 0x2011
#define DF_DIAG_32BIT_CRC 0x80000000
#define DF_OUTPUT_CRT 0x00000000
#define DF_OUTPUT_PANEL 0x00000008
#define DF_OUTPUT_VOP 0x00000030
#define DF_OUTPUT_DRGB 0x00000038
#define DF_SIMULTANEOUS_CRT_FP 0x00008000
#define DF_CONFIG_OUTPUT_MASK 0x00000038
/*----------------------------------------------------------------*/
/* MSR DEFINITIONS */
/*----------------------------------------------------------------*/
/*----------------------------*/
/* STATIC GEODELINK ADRESSES */
/*----------------------------*/
#define MSR_ADDRESS_GLIU0 0x10000000
#define MSR_ADDRESS_GLIU1 0x40000000
#define MSR_ADDRESS_GLIU2 0x51010000
#define MSR_ADDRESS_5535MPCI 0x51000000
#define MSR_ADDRESS_VAIL 0x00000000
/*----------------------------*/
/* UNIVERSAL DEVICE MSRS */
/*----------------------------*/
#define MSR_GEODELINK_CAP 0x2000
#define MSR_GEODELINK_CONFIG 0x2001
#define MSR_GEODELINK_SMI 0x2002
#define MSR_GEODELINK_ERROR 0x2003
#define MSR_GEODELINK_PM 0x2004
#define MSR_GEODELINK_DIAG 0x2005
/*----------------------------*/
/* DEVICE CLASS CODES */
/*----------------------------*/
#define MSR_CLASS_CODE_GLIU 0x01
#define MSR_CLASS_CODE_GLCP 0x02
#define MSR_CLASS_CODE_MPCI 0x05
#define MSR_CLASS_CODE_MC 0x20
#define MSR_CLASS_CODE_GP 0x3D
#define MSR_CLASS_CODE_VG 0x3E
#define MSR_CLASS_CODE_DF 0x3F
#define MSR_CLASS_CODE_FG 0xF0
#define MSR_CLASS_CODE_VAIL 0x86
#define MSR_CLASS_CODE_USB 0x42
#define MSR_CLASS_CODE_USB2 0x43
#define MSR_CLASS_CODE_ATAC 0x47
#define MSR_CLASS_CODE_MDD 0xDF
#define MSR_CLASS_CODE_ACC 0x33
#define MSR_CLASS_CODE_AES 0x30
#define MSR_CLASS_CODE_VIP 0x3C
#define MSR_CLASS_CODE_REFLECTIVE 0xFFF
#define MSR_CLASS_CODE_UNPOPULATED 0x7FF
/*----------------------------*/
/* GLIU MSR DEFINITIONS */
/*----------------------------*/
#define MSR_GLIU_CAP 0x0086
#define MSR_GLIU_WHOAMI 0x008B
#define NUM_PORTS_MASK 0x00380000
#define NUM_PORTS_SHIFT 19
#define WHOAMI_MASK 0x07
/*----------------------------*/
/* GLCP MSR DEFINITIONS */
/*----------------------------*/
#define GLCP_CLKOFF 0x0010
#define GLCP_CLKACTIVE 0x0011
#define GLCP_CLKDISABLE 0x0012
#define GLCP_CLK4ACK 0x0013
#define GLCP_SYS_RSTPLL 0x0014
#define GLCP_DOTPLL 0x0015
#define GLCP_DBGCLKCTL 0x0016
#define GLCP_REVID 0x0017
#define GLCP_RAW_DIAG 0x0028
#define GLCP_SETM0CTL 0x0040
#define GLCP_SETN0CTL 0x0048
#define GLCP_CMPVAL0 0x0050
#define GLCP_CMPMASK0 0x0051
#define GLCP_REGA 0x0058
#define GLCP_REGB 0x0059
#define GLCP_REGAMASK 0x005A
#define GLCP_REGAVAL 0x005B
#define GLCP_REGBMASK 0x005C
#define GLCP_REGBVAL 0x005D
#define GLCP_FIFOCTL 0x005E
#define GLCP_DIAGCTL 0x005F
#define GLCP_H0CTL 0x0060
#define GLCP_XSTATE 0x0066
#define GLCP_YSTATE 0x0067
#define GLCP_ACTION0 0x0068
/* GLCP_DOTPLL DEFINITIONS */
#define GLCP_DOTPLL_RESET 0x00000001
#define GLCP_DOTPLL_BYPASS 0x00008000
#define GLCP_DOTPLL_HALFPIX 0x01000000
#define GLCP_DOTPLL_LOCK 0x02000000
#define GLCP_DOTPLL_VIPCLK 0x00008000
#define GLCP_DOTPLL_DIV4 0x00010000
/* GLCP DIAG DEFINITIONS */
#define GLCP_MBD_DIAG_SEL0 0x00000007
#define GLCP_MBD_DIAG_EN0 0x00008000
#define GLCP_MBD_DIAG_SEL1 0x00070000
#define GLCP_MBD_DIAG_EN1 0x80000000
/*--------------------------------*/
/* DISPLAY FILTER MSR DEFINITIONS */
/*--------------------------------*/
/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */
#define DF_MBD_DIAG_SEL0 0x00007FFF
#define DF_MBD_DIAG_EN0 0x00008000
#define DF_MBD_DIAG_SEL1 0x7FFF0000
#define DF_MBD_DIAG_EN1 0x80000000
/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */
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