cim_regs.h

LX 800 WindowsCE 6.0 BSP

#define DC3_FILT_COEFF1                     0x00000098
#define DC3_FILT_COEFF2                     0x0000009C

#define DC3_VBI_EVEN_CTL                    0x000000A0  /* VBI Data Buffer Controls      */
#define DC3_VBI_ODD_CTL                     0x000000A4
#define DC3_VBI_HOR                         0x000000A8
#define DC3_VBI_LN_ODD                      0x000000AC
#define DC3_VBI_LN_EVEN                     0x000000B0
#define DC3_VBI_PITCH                       0x000000B4

#define DC3_COLOR_KEY                       0x000000B8  /* Graphics color key            */
#define DC3_COLOR_MASK                      0x000000BC  /* Graphics color key mask       */
#define DC3_CLR_KEY_X                       0x000000C0
#define DC3_CLR_KEY_Y                       0x000000C4

#define DC3_IRQ                             0x000000C8
#define DC3_GENLK_CTL                       0x000000D4

#define DC3_VID_EVEN_Y_ST_OFFSET            0x000000D8  /* Even field video buffers      */
#define DC3_VID_EVEN_U_ST_OFFSET            0x000000DC
#define DC3_VID_EVEN_V_ST_OFFSET            0x000000E0

#define DC3_V_ACTIVE_EVEN                   0x000000E4  /* Even field timing registers   */
#define DC3_V_BLANK_EVEN                    0x000000E8
#define DC3_V_SYNC_EVEN                     0x000000EC

/* UNLOCK VALUE */

#define DC3_UNLOCK_VALUE		            0x00004758		/* used to unlock DC regs	*/

/* VG GEODELINK DEVICE SMI MSR FIELDS */

#define DC3_VG_BL_MASK                      0x00000001
#define DC3_MISC_MASK                       0x00000002
#define DC3_ISR0_MASK                       0x00000004
#define DC3_VGA_BL_MASK                     0x00000008
#define DC3_CRTCIO_MSK                      0x00000010
#define DC3_VG_BLANK_SMI                    0x00000001
#define DC3_MISC_SMI                        0x00000002
#define DC3_ISR0_SMI                        0x00000004
#define DC3_VGA_BLANK_SMI                   0x00000008
#define DC3_CRTCIO_SMI                      0x00000010

/* DC3_GENERAL_CFG BIT FIELDS */

#define DC3_GCFG_DBUG                       0x80000000
#define DC3_GCFG_DBSL                       0x40000000
#define DC3_GCFG_CFRW                       0x20000000
#define DC3_GCFG_DIAG                       0x10000000
#define DC3_GCFG_CRC_MODE                   0x08000000
#define DC3_GCFG_SGFR                       0x04000000
#define DC3_GCFG_SGRE                       0x02000000
#define DC3_GCFG_SIGE                       0x01000000
#define DC3_GCFG_SIG_SEL                    0x00800000
#define DC3_GCFG_YUV_420                    0x00100000
#define DC3_GCFG_VDSE                       0x00080000
#define DC3_GCFG_VGAFT                      0x00040000
#define DC3_GCFG_FDTY                       0x00020000
#define DC3_GCFG_STFM                       0x00010000
#define DC3_GCFG_DFHPEL_MASK                0x0000F000
#define DC3_GCFG_DFHPSL_MASK                0x00000F00
#define DC3_GCFG_VGAE                       0x00000080
#define DC3_GCFG_DECE                       0x00000040
#define DC3_GCFG_CMPE                       0x00000020
#define DC3_GCFG_FILT_SIG_SEL               0x00000010
#define DC3_GCFG_VIDE                       0x00000008
#define DC3_GCFG_CLR_CUR                    0x00000004
#define DC3_GCFG_CURE                       0x00000002
#define DC3_GCFG_DFLE                       0x00000001

/* DC3_DISPLAY_CFG BIT FIELDS */

#define DC3_DCFG_VISL                       0x08000000
#define DC3_DCFG_FRLK                       0x04000000
#define DC3_DCFG_PALB                       0x02000000
#define DC3_DCFG_DCEN                       0x01000000
#define DC3_DCFG_VFHPEL_MASK                0x000F0000
#define DC3_DCFG_VFHPSL_MASK                0x0000F000
#define DC3_DCFG_16BPP_MODE_MASK            0x00000C00
#define DC3_DCFG_16BPP                      0x00000000
#define DC3_DCFG_15BPP                      0x00000400
#define DC3_DCFG_12BPP                      0x00000800
#define DC3_DCFG_DISP_MODE_MASK             0x00000300
#define DC3_DCFG_DISP_MODE_8BPP             0x00000000
#define DC3_DCFG_DISP_MODE_16BPP            0x00000100
#define DC3_DCFG_DISP_MODE_24BPP            0x00000200
#define DC3_DCFG_DISP_MODE_32BPP            0x00000300
#define DC3_DCFG_TRUP                       0x00000040
#define DC3_DCFG_VDEN                       0x00000010
#define DC3_DCFG_GDEN                       0x00000008
#define DC3_DCFG_TGEN                       0x00000001

/* DC3_ARB_CFG BIT FIELDS */

#define DC3_ACFG_LB_LOAD_WM_EN              0x00100000
#define DC3_ACFG_LB_LOAD_WM_MASK            0x000F0000
#define DC3_ACFG_LPEN_END_COUNT_MASK        0x0000FE00
#define DC3_ACFG_HPEN_SBINV                 0x00000100
#define DC3_ACFG_HPEN_FB_INV_HALFSB         0x00000080
#define DC3_ACFG_HPEN_FB_INV_SBRD           0x00000040
#define DC3_ACFG_HPEN_FB_INV                0x00000020
#define DC3_ACFG_HPEN_1LB_INV               0x00000010
#define DC3_ACFG_HPEN_2LB_INV               0x00000008
#define DC3_ACFG_HPEN_3LB_INV               0x00000004
#define DC3_ACFG_HPEN_LB_FILL               0x00000002
#define DC3_ACFG_LPEN_VSYNC                 0x00000001

/* DC3_FB_ST_OFFSET BIT FIELDS */

#define DC3_FB_ST_OFFSET_MASK               0x0FFFFFFF

/* DC3_CB_ST_OFFSET BIT FIELDS */

#define DC3_CB_ST_OFFSET_MASK               0x0FFFFFFF

/* DC3_CURS_ST_OFFSET BIT FIELDS */

#define DC3_CURS_ST_OFFSET_MASK             0x0FFFFFFF

/* DC3_ICON_ST_OFFSET BIT FIELDS */

#define DC3_ICON_ST_OFFSET_MASK             0x0FFFFFFF

/* DC3_VID_Y_ST_OFFSET BIT FIELDS */

#define DC3_VID_Y_ST_OFFSET_MASK            0x0FFFFFFF

/* DC3_VID_U_ST_OFFSET BIT FIELDS */

#define DC3_VID_U_ST_OFFSET_MASK            0x0FFFFFFF

/* DC3_VID_V_ST_OFFSET BIT FIELDS */

#define DC3_VID_V_ST_OFFSET_MASK            0x0FFFFFFF

/* DC3_DV_TOP BIT FIELDS */

#define DC3_DVTOP_ENABLE                    0x00000001
#define DC3_DVTOP_MAX_MASK                  0x00FFFC00
#define DC3_DVTOP_MAX_SHIFT                 10

/* DC3_LINE_SIZE BIT FIELDS */

#define DC3_LINE_SIZE_VLS_MASK              0x3FF00000
#define DC3_LINE_SIZE_CBLS_MASK             0x0007F000
#define DC3_LINE_SIZE_FBLS_MASK             0x000003FF
#define DC3_LINE_SIZE_CB_SHIFT              12
#define DC3_LINE_SIZE_VB_SHIFT              20

/* DC3_GFX_PITCH BIT FIELDS */

#define DC3_GFX_PITCH_CBP_MASK              0xFFFF0000
#define DC3_GFX_PITCH_FBP_MASK              0x0000FFFF

/* DC3_VID_YUV_PITCH BIT FIELDS */

#define DC3_YUV_PITCH_UVP_MASK              0xFFFF0000
#define DC3_YUV_PITCH_YBP_MASK              0x0000FFFF

/* DC3_H_ACTIVE_TIMING BIT FIELDS */

#define DC3_HAT_HT_MASK                     0x0FF80000
#define DC3_HAT_HA_MASK                     0x00000FF8

/* DC3_H_BLANK_TIMING BIT FIELDS */

#define DC3_HBT_HBE_MASK                    0x0FF80000
#define DC3_HBT_HBS_MASK                    0x00000FF8

/* DC3_H_SYNC_TIMING BIT FIELDS */

#define DC3_HST_HSE_MASK                    0x0FF80000
#define DC3_HST_HSS_MASK                    0x00000FF8

/* DC3_V_ACTIVE_TIMING BIT FIELDS */

#define DC3_VAT_VT_MASK                     0x07FF0000
#define DC3_VAT_VA_MASK                     0x000007FF

/* DC3_V_BLANK_TIMING BIT FIELDS */

#define DC3_VBT_VBE_MASK                    0x07FF0000
#define DC3_VBT_VBS_MASK                    0x000007FF

/* DC3_V_SYNC_TIMING BIT FIELDS */

#define DC3_VST_VSE_MASK                    0x07FF0000
#define DC3_VST_VSS_MASK                    0x000007FF

/* DC3_LINE_CNT_STATUS BIT FIELDS     */

#define DC3_LNCNT_DNA                       0x80000000
#define DC3_LNCNT_VNA                       0x40000000
#define DC3_LNCNT_VSA                       0x20000000
#define DC3_LNCNT_VINT                      0x10000000
#define DC3_LNCNT_FLIP                      0x08000000
#define DC3_LNCNT_V_LINE_CNT                0x07FF0000
#define DC3_LNCNT_VFLIP                     0x00008000
#define DC3_LNCNT_SIGC                      0x00004000
#define DC3_LNCNT_EVEN_FIELD                0x00002000
#define DC3_LNCNT_SS_LINE_CMP               0x000007FF

/* DC3_VID_DS_DELTA BIT FIELDS */

#define DC3_DS_DELTA_MASK                   0xFFFC0000
#define DC3_601_VSYNC_SHIFT_MASK            0x00000FFF
#define DC3_601_VSYNC_SHIFT_ENABLE          0x00008000

/* DC3_DV_CTL BIT DEFINITIONS */

#define DC3_DV_LINE_SIZE_MASK               0x00000C00
#define DC3_DV_LINE_SIZE_1024               0x00000000
#define DC3_DV_LINE_SIZE_2048               0x00000400
#define DC3_DV_LINE_SIZE_4096               0x00000800
#define DC3_DV_LINE_SIZE_8192               0x00000C00

/* DC3_IRQ_FILT_CTL DEFINITIONS */

#define DC3_IRQFILT_LB_MASK                 0x80000200
#define DC3_IRQFILT_LB_COEFF                0x00000000
#define DC3_IRQFILT_SCALER_FILTER           0x00000200
#define DC3_IRQFILT_SYNCHRONIZER            0x80000000
#define DC3_IRQFILT_FLICKER_FILTER          0x80000200
#define DC3_IRQFILT_LB_SEL_MASK             0x60000000
#define DC3_IRQFILT_INTL_ADDR               0x10000000
#define DC3_IRQFILT_LINE_MASK               0x07FF0000
#define DC3_IRQFILT_ALPHA_FILT_EN           0x00004000
#define DC3_IRQFILT_GFX_FILT_EN             0x00001000
#define DC3_IRQFILT_INTL_EN                 0x00000800
#define DC3_IRQFILT_H_FILT_SEL              0x00000400
#define DC3_IRQFILT_LB_ADDR                 0x00000100

/* DC3_VBI_EVEN_CTL DEFINITIONS */

#define DC3_VBI_EVEN_ENABLE_CRC             (1L << 31)
#define DC3_VBI_EVEN_CTL_ENABLE_16          (1L << 30)
#define DC3_VBI_EVEN_CTL_UPSCALE            (1L << 29)
#define DC3_VBI_ENABLE                      (1L << 28)
#define DC3_VBI_EVEN_CTL_OFFSET_MASK        0x0FFFFFFF

/* DC3_VBI_ODD_CTL DEFINITIONS */

#define DC3_VBI_ODD_CTL_OFFSET_MASK         0x0FFFFFFF

/* DC3_VBI_HOR BIT DEFINITIONS */

#define DC3_VBI_HOR_END_SHIFT               16
#define DC3_VBI_HOR_END_MASK				0x0FFF0000
#define DC3_VBI_HOR_START_MASK				0x00000FFF

/* DC3_VBI_LN_ODD BIT DEFINITIONS */

#define DC3_VBI_ODD_ENABLE_SHIFT            2
#define DC3_VBI_ODD_ENABLE_MASK             0x01FFFFFC
#define DC3_VBI_ODD_LINE_SHIFT              25
#define DC3_VBI_ODD_LINE_MASK               0xFE000000

/* DC3_VBI_LN_EVEN BIT DEFINITIONS */

#define DC3_VBI_EVEN_ENABLE_SHIFT           2
#define DC3_VBI_EVEN_ENABLE_MASK			0x01FFFFFC
#define DC3_VBI_EVEN_LINE_SHIFT             25
#define DC3_VBI_EVEN_LINE_MASK				0xFE000000

/* DC3_COLOR_KEY DEFINITIONS */

#define DC3_CLR_KEY_DATA_MASK               0x00FFFFFF
#define DC3_CLR_KEY_ENABLE                  0x01000000

/* DC3_IRQ DEFINITIONS */

#define DC3_IRQ_MASK                        0x00000001
#define DC3_VSYNC_IRQ_MASK                  0x00000002
#define DC3_IRQ_STATUS                      0x00010000
#define DC3_VSYNC_IRQ_STATUS                0x00020000

/* DC3_GENLK_CTL DEFINITIONS */

#define DC3_GC_FLICKER_FILTER_NONE          0x00000000
#define DC3_GC_FLICKER_FILTER_1_16          0x10000000
#define DC3_GC_FLICKER_FILTER_1_8           0x20000000
#define DC3_GC_FLICKER_FILTER_1_4           0x40000000
#define DC3_GC_FLICKER_FILTER_5_16          0x50000000
#define DC3_GC_FLICKER_FILTER_MASK          0xF0000000
#define DC3_GC_ALPHA_FLICK_ENABLE           0x02000000
#define DC3_GC_FLICKER_FILTER_ENABLE        0x01000000
#define DC3_GC_VIP_VID_OK                   0x00800000
#define DC3_GC_GENLK_ACTIVE                 0x00400000
#define DC3_GC_SKEW_WAIT                    0x00200000
#define DC3_GC_VSYNC_WAIT                   0x00100000
#define DC3_GC_GENLOCK_TO_ENABLE            0x00080000
#define DC3_GC_GENLOCK_ENABLE               0x00040000
#define DC3_GC_GENLOCK_SKEW_MASK            0x0003FFFF

/* VGA DEFINITIONS */

#define DC3_SEQUENCER_INDEX                 0x03C4
#define DC3_SEQUENCER_DATA                  0x03C5
#define DC3_SEQUENCER_RESET                 0x00
#define DC3_SEQUENCER_CLK_MODE              0x01

#define DC3_RESET_VGA_DISP_ENABLE           0x03
#define DC3_CLK_MODE_SCREEN_OFF             0x20

/* DOT CLOCK FREQUENCY STRUCTURE */
/* Note that m, n and p refer to the register m, n and p  */
/* and not the m, n and p from the PLL equation.  The PLL */
/* equation adds 1 to each value.                         */