📄 cim_regs.h
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/*
* <LIC_AMD_STD>
* Copyright (C) 2005 Advanced Micro Devices, Inc. All Rights Reserved.
* </LIC_AMD_STD>
*
* <CTL_AMD_STD>
* </CTL_AMD_STD>
*
* <DOC_AMD_STD>
* Cimarron register definitions
* </DOC_AMD_STD>
*
*/
#ifndef _cim_regs_h
#define _cim_regs_h
/*----------------------------------------------------------------*/
/* GRAPHICS PROCESSOR DEFINITIONS */
/*----------------------------------------------------------------*/
/*----------------------------*/
/* COMMAND BUFFER DEFINITIONS */
/*----------------------------*/
#define GP3_BLT_COMMAND_SIZE 68 /* 18 DWORDS */
#define GP3_VECTOR_COMMAND_SIZE 56 /* 14 DWORDS */
#define GP3_4BPP_LUT_COMMAND_SIZE 76 /* 16 DWORDS + 3 CMD DWORDS */
#define GP3_8BPP_LUT_COMMAND_SIZE 1036 /* 256 DWORDS + 3 CMD DWORDS */
#define GP3_VECTOR_PATTERN_COMMAND_SIZE 20 /* 2 DWORDS + 3 CMD DWORDS */
#define GP3_MAX_COMMAND_SIZE 9000 /* 8K + WORKAROUND SPACE */
#define GP3_SCRATCH_BUFFER_SIZE 0x100000 /* 1MB SCRATCH BUFFER */
#define GP3_BLT_1PASS_SIZE 0xC7F8 /* (50K - 8) is largest 1-Pass load size */
/*-------------------------------------*/
/* BLT COMMAND BUFFER REGISTER OFFSETS */
/*-------------------------------------*/
#define GP3_BLT_CMD_HEADER 0x00000000
#define GP3_BLT_RASTER_MODE 0x00000004
#define GP3_BLT_DST_OFFSET 0x00000008
#define GP3_BLT_SRC_OFFSET 0x0000000C
#define GP3_BLT_STRIDE 0x00000010
#define GP3_BLT_WID_HEIGHT 0x00000014
#define GP3_BLT_SRC_COLOR_FG 0x00000018
#define GP3_BLT_SRC_COLOR_BG 0x0000001C
#define GP3_BLT_PAT_COLOR_0 0x00000020
#define GP3_BLT_PAT_COLOR_1 0x00000024
#define GP3_BLT_PAT_DATA_0 0x00000028
#define GP3_BLT_PAT_DATA_1 0x0000002C
#define GP3_BLT_CH3_OFFSET 0x00000030
#define GP3_BLT_CH3_MODE_STR 0x00000034
#define GP3_BLT_CH3_WIDHI 0x00000038
#define GP3_BLT_BASE_OFFSET 0x0000003C
#define GP3_BLT_MODE 0x00000040
/*-----------------------------------------------------------------*/
/* VECTOR COMMAND BUFFER REGISTER OFFSETS */
/* Some of these are identical to the BLT registers (and we will */
/* be assumed to be such in the Cimarron code, but they are listed */
/* here for clarity and for future changes. */
/*-----------------------------------------------------------------*/
#define GP3_VEC_CMD_HEADER 0x00000000
#define GP3_VECTOR_RASTER_MODE 0x00000004
#define GP3_VECTOR_DST_OFFSET 0x00000008
#define GP3_VECTOR_VEC_ERR 0x0000000C
#define GP3_VECTOR_STRIDE 0x00000010
#define GP3_VECTOR_VEC_LEN 0x00000014
#define GP3_VECTOR_SRC_COLOR_FG 0x00000018
#define GP3_VECTOR_PAT_COLOR_0 0x0000001C
#define GP3_VECTOR_PAT_COLOR_1 0x00000020
#define GP3_VECTOR_PAT_DATA_0 0x00000024
#define GP3_VECTOR_PAT_DATA_1 0x00000028
#define GP3_VECTOR_CH3_MODE_STR 0x0000002C
#define GP3_VECTOR_BASE_OFFSET 0x00000030
#define GP3_VECTOR_MODE 0x00000034
/*---------------------------------------------------*/
/* GP REGISTER DEFINITIONS */
/* Addresses for writing or reading directly to/from */
/* the graphics processor. */
/*---------------------------------------------------*/
#define GP3_DST_OFFSET 0x00000000
#define GP3_SRC_OFFSET 0x00000004
#define GP3_VEC_ERR 0x00000004
#define GP3_STRIDE 0x00000008
#define GP3_WID_HEIGHT 0x0000000C
#define GP3_VEC_LEN 0x0000000C
#define GP3_SRC_COLOR_FG 0x00000010
#define GP3_SRC_COLOR_BG 0x00000014
#define GP3_PAT_COLOR_0 0x00000018
#define GP3_PAT_COLOR_1 0x0000001C
#define GP3_PAT_COLOR_2 0x00000020
#define GP3_PAT_COLOR_3 0x00000024
#define GP3_PAT_COLOR_4 0x00000028
#define GP3_PAT_COLOR_5 0x0000002C
#define GP3_PAT_DATA_0 0x00000030
#define GP3_PAT_DATA_1 0x00000034
#define GP3_RASTER_MODE 0x00000038
#define GP3_VEC_MODE 0x0000003C
#define GP3_BLT_MODE 0x00000040
#define GP3_BLT_STATUS 0x00000044
#define GP3_HST_SRC 0x00000048
#define GP3_BASE_OFFSET 0x0000004C
#define GP3_CMD_TOP 0x00000050
#define GP3_CMD_BOT 0x00000054
#define GP3_CMD_READ 0x00000058
#define GP3_CMD_WRITE 0x0000005C
#define GP3_CH3_OFFSET 0x00000060
#define GP3_CH3_MODE_STR 0x00000064
#define GP3_CH3_WIDHI 0x00000068
#define GP3_CH3_HST_SRC 0x0000006C
#define GP3_LUT_ADDRESS 0x00000070
#define GP3_LUT_DATA 0x00000074
#define GP3_INT_CTL 0x00000078
#define GP3_HST_SRC_RANGE 0x00000100
/*------------------------*/
/* REGISTER BIT FIELDS */
/*------------------------*/
/* GP3_BLT_CMD_HEADER BIT DEFINITIONS */
#define GP3_BLT_HDR_WRAP 0x80000000
#define GP3_BLT_HDR_TYPE 0x00000000
#define GP3_BLT_HDR_HAZARD_ENABLE 0x10000000
#define GP3_BLT_HDR_RASTER_ENABLE 0x00000001
#define GP3_BLT_HDR_DST_OFF_ENABLE 0x00000002
#define GP3_BLT_HDR_SRC_OFF_ENABLE 0x00000004
#define GP3_BLT_HDR_STRIDE_ENABLE 0x00000008
#define GP3_BLT_HDR_WIDHI_ENABLE 0x00000010
#define GP3_BLT_HDR_SRC_FG_ENABLE 0x00000020
#define GP3_BLT_HDR_SRC_BG_ENABLE 0x00000040
#define GP3_BLT_HDR_PAT_CLR0_ENABLE 0x00000080
#define GP3_BLT_HDR_PAT_CLR1_ENABLE 0x00000100
#define GP3_BLT_HDR_PAT_DATA0_ENABLE 0x00000200
#define GP3_BLT_HDR_PAT_DATA1_ENABLE 0x00000400
#define GP3_BLT_HDR_CH3_OFF_ENABLE 0x00000800
#define GP3_BLT_HDR_CH3_STR_ENABLE 0x00001000
#define GP3_BLT_HDR_CH3_WIDHI_ENABLE 0x00002000
#define GP3_BLT_HDR_BASE_OFFSET_ENABLE 0x00004000
#define GP3_BLT_HDR_BLT_MODE_ENABLE 0x00008000
/* GP3_VEC_CMD_HEADER BIT DEFINITIONS */
#define GP3_VEC_HDR_WRAP 0x80000000
#define GP3_VEC_HDR_TYPE 0x20000000
#define GP3_VEC_HDR_HAZARD_ENABLE 0x10000000
#define GP3_VEC_HDR_RASTER_ENABLE 0x00000001
#define GP3_VEC_HDR_DST_OFF_ENABLE 0x00000002
#define GP3_VEC_HDR_VEC_ERR_ENABLE 0x00000004
#define GP3_VEC_HDR_STRIDE_ENABLE 0x00000008
#define GP3_VEC_HDR_VEC_LEN_ENABLE 0x00000010
#define GP3_VEC_HDR_SRC_FG_ENABLE 0x00000020
#define GP3_VEC_HDR_PAT_CLR0_ENABLE 0x00000040
#define GP3_VEC_HDR_PAT_CLR1_ENABLE 0x00000080
#define GP3_VEC_HDR_PAT_DATA0_ENABLE 0x00000100
#define GP3_VEC_HDR_PAT_DATA1_ENABLE 0x00000200
#define GP3_VEC_HDR_CH3_STR_ENABLE 0x00000400
#define GP3_VEC_HDR_BASE_OFFSET_ENABLE 0x00000800
#define GP3_VEC_HDR_VEC_MODE_ENABLE 0x00001000
/* GP3_RASTER_MODE BIT DEFINITIONS */
#define GP3_RM_BPPFMT_332 0x00000000 /* 8 BPP, palettized */
#define GP3_RM_BPPFMT_4444 0x40000000 /* 16 BPP, 4:4:4:4 */
#define GP3_RM_BPPFMT_1555 0x50000000 /* 16 BPP, 1:5:5:5 */
#define GP3_RM_BPPFMT_565 0x60000000 /* 16 BPP, 5:6:5 */
#define GP3_RM_BPPFMT_8888 0x80000000 /* 32 BPP, 8:8:8:8 */
#define GP3_RM_ALPHA_ALL 0x00C00000 /* Alpha enable */
#define GP3_RM_ALPHA_TO_RGB 0x00400000 /* Alpha applies to RGB */
#define GP3_RM_ALPHA_TO_ALPHA 0x00800000 /* Alpha applies to alpha */
#define GP3_RM_ALPHA_OP_MASK 0x00300000 /* Alpha operation */
#define GP3_RM_ALPHA_TIMES_A 0x00000000 /* Alpha * A */
#define GP3_RM_BETA_TIMES_B 0x00100000 /* (1-alpha) * B */
#define GP3_RM_A_PLUS_BETA_B 0x00200000 /* A + (1-alpha) * B */
#define GP3_RM_ALPHA_A_PLUS_BETA_B 0x00300000 /* alpha * A + (1 - alpha)B */
#define GP3_RM_ALPHA_SELECT 0x000E0000 /* Alpha Select */
#define GP3_RM_SELECT_ALPHA_A 0x00000000 /* Alpha from channel A */
#define GP3_RM_SELECT_ALPHA_B 0x00020000 /* Alpha from channel B */
#define GP3_RM_SELECT_ALPHA_R 0x00040000 /* Registered alpha */
#define GP3_RM_SELECT_ALPHA_1 0x00060000 /* Constant 1 */
#define GP3_RM_SELECT_ALPHA_CHAN_A 0x00080000 /* RGB Values from A */
#define GP3_RM_SELECT_ALPHA_CHAN_B 0x000A0000 /* RGB Values from B */
#define GP3_RM_SELECT_ALPHA_CHAN_3 0x000C0000 /* Alpha from channel 3 */
#define GP3_RM_DEST_FROM_CHAN_A 0x00010000 /* Alpha channel select */
#define GP3_RM_PATTERN_INVERT 0x00001000 /* Invert monochrome pat */
#define GP3_RM_SOURCE_INVERT 0x00002000 /* Invert monochrome src */
#define GP3_RM_PAT_FLAGS 0x00000700 /* pattern related bits */
#define GP3_RM_PAT_MONO 0x00000100 /* monochrome pattern */
#define GP3_RM_PAT_COLOR 0x00000200 /* color pattern */
#define GP3_RM_PAT_TRANS 0x00000400 /* pattern transparency */
#define GP3_RM_SRC_TRANS 0x00000800 /* source transparency */
/* GP3_VECTOR_MODE REGISTER DESCRIPTIONS */
#define GP3_VM_DST_REQ 0x00000008 /* dst data required */
#define GP3_VM_THROTTLE 0x00000010 /* sync to VBLANK */
/* GP3_BLT_MODE REGISTER DEFINITIONS */
#define GP3_BM_SRC_FB 0x00000001 /* src = frame buffer */
#define GP3_BM_SRC_HOST 0x00000002 /* src = host register */
#define GP3_BM_DST_REQ 0x00000004 /* dst data required */
#define GP3_BM_SRC_MONO 0x00000040 /* monochrome source data */
#define GP3_BM_SRC_BP_MONO 0x00000080 /* Byte-packed monochrome */
#define GP3_BM_NEG_YDIR 0x00000100 /* negative Y direction */
#define GP3_BM_NEG_XDIR 0x00000200 /* negative X direction */
#define GP3_BM_THROTTLE 0x00000400 /* sync to VBLANK */
/* GP3_BLT_STATUS REGISTER DEFINITIONS */
#define GP3_BS_BLT_BUSY 0x00000001 /* GP is not idle */
#define GP3_BS_BLT_PENDING 0x00000004 /* second BLT is pending */
#define GP3_BS_HALF_EMPTY 0x00000008 /* src FIFO half empty */
#define GP3_BS_CB_EMPTY 0x00000010 /* Command buffer empty. */
/* GP3_CH3_MODE_STR REGISTER DEFINITIONS */
#define GP3_CH3_C3EN 0x80000000
#define GP3_CH3_REPLACE_SOURCE 0x40000000
#define GP3_CH3_NEG_XDIR 0x20000000
#define GP3_CH3_NEG_YDIR 0x10000000
#define GP3_CH3_SRC_FMT_MASK 0x0f000000
#define GP3_CH3_SRC_3_3_2 0x00000000
#define GP3_CH3_SRC_8BPP_INDEXED 0x01000000
#define GP3_CH3_SRC_8BPP_ALPHA 0x02000000
#define GP3_CH3_SRC_4_4_4_4 0x04000000
#define GP3_CH3_SRC_1_5_5_5 0x05000000
#define GP3_CH3_SRC_0_5_6_5 0x06000000
#define GP3_CH3_SRC_Y_U_V 0x07000000
#define GP3_CH3_SRC_8_8_8_8 0x08000000
#define GP3_CH3_SRC_24BPP_PACKED 0x0B000000
#define GP3_CH3_SRC_4BPP_INDEXED 0x0D000000
#define GP3_CH3_SRC_4BPP_ALPHA 0x0E000000
#define GP3_CH3_SRC_MASK 0x0F000000
#define GP3_CH3_ROTATE_ENABLE 0x00800000
#define GP3_CH3_BGR_ORDER 0x00400000
#define GP3_CH3_COLOR_PAT_ENABLE 0x00200000
#define GP3_CH3_PRESERVE_LUT 0x00100000
#define GP3_CH3_PREFETCH_ENABLE 0x00080000
#define GP3_CH3_HST_SRC_ENABLE 0x00040000
#define GP3_CH3_STRIDE_MASK 0x0000FFFF
/* DATA AND LUT LOAD BIT DEFINITIONS */
#define GP3_LUT_HDR_WRAP 0x80000000
#define GP3_LUT_HDR_TYPE 0x40000000
#define GP3_LUT_HDR_DATA_ENABLE 0x00000003
#define GP3_DATA_LOAD_HDR_WRAP 0x80000000
#define GP3_DATA_LOAD_HDR_TYPE 0x60000000
#define GP3_DATA_LOAD_HDR_ENABLE 0x00000001
#define GP3_HOST_SOURCE_TYPE 0x00000000
#define GP3_CH3_HOST_SOURCE_TYPE 0x20000000
#define GP3_OLD_PATTERN_COLORS 0x40000000
#define GP3_LUT_DATA_TYPE 0x60000000
#define GP3_BASE_OFFSET_DSTMASK 0xFFC00000
#define GP3_BASE_OFFSET_SRCMASK 0x003FF000
#define GP3_BASE_OFFSET_CH3MASK 0x00000FFC
/*----------------------------------------------------------------*/
/* VIDEO GENERATOR DEFINITIONS */
/*----------------------------------------------------------------*/
#define DC3_UNLOCK 0x00000000 /* Unlock register */
#define DC3_GENERAL_CFG 0x00000004 /* Config registers */
#define DC3_DISPLAY_CFG 0x00000008
#define DC3_ARB_CFG 0x0000000C
#define DC3_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */
#define DC3_CB_ST_OFFSET 0x00000014 /* Compression start offset */
#define DC3_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start offset */
#define DC3_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start offset */
#define DC3_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start offset */
#define DC3_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start offset */
#define DC3_DV_TOP 0x0000002C /* DV Ram Limit Register */
#define DC3_LINE_SIZE 0x00000030 /* Video, CB, and FB line sizes */
#define DC3_GFX_PITCH 0x00000034 /* FB and DB skip counts */
#define DC3_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip counts */
#define DC3_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */
#define DC3_H_BLANK_TIMING 0x00000044
#define DC3_H_SYNC_TIMING 0x00000048
#define DC3_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */
#define DC3_V_BLANK_TIMING 0x00000054
#define DC3_V_SYNC_TIMING 0x00000058
#define DC3_FB_ACTIVE 0x0000005C
#define DC3_CURSOR_X 0x00000060 /* Cursor X position */
#define DC3_CURSOR_Y 0x00000064 /* Cursor Y Position */
#define DC3_LINE_CNT_STATUS 0x0000006C
#define DC3_PAL_ADDRESS 0x00000070 /* Palette Address */
#define DC3_PAL_DATA 0x00000074 /* Palette Data */
#define DC3_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */
#define DC3_CFIFO_DIAG 0x0000007C /* Compression FIFO diagnostic */
#define DC3_VID_DS_DELTA 0x00000080 /* Vertical Downscaling fraction */
#define DC3_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */
#define DC3_DV_CTL 0x00000088 /* Dirty-Valid Control Register */
#define DC3_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */
#define DC3_GFX_SCALE 0x00000090 /* Graphics Scaling */
#define DC3_IRQ_FILT_CTL 0x00000094 /* VBlank interrupt and filters */
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