cim_df.c

LX 800 WindowsCE 6.0 BSP

	for (i = 0; i < 256; i++)
        df_state->palette[i] = READ_VID32 (DF_PALETTE_DATA);

    /* READ FILTER COEFFICIENTS */

    for (i = 0; i < 512; i++)
        df_state->coefficients[i] = READ_VID32 (DF_COEFFICIENT_BASE + (i << 2));

    /* READ ALL DF MSRS */

    msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CAP,    &(df_state->msr_cap));
    msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &(df_state->msr_config));
    msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_SMI,    &(df_state->msr_smi));
    msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_ERROR,  &(df_state->msr_error));
    msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_PM,     &(df_state->msr_pm));
    msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_DIAG,   &(df_state->msr_diag));
    msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF,   &(df_state->msr_df_diag));
    msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL,       &(df_state->msr_pad_sel));

    return CIM_STATUS_OK;
}

/*---------------------------------------------------------------------------
 * df_restore_state
 *
 * This routine restores all persistent DF state information.
 *---------------------------------------------------------------------------*/

int df_restore_state (DF_SAVE_RESTORE *df_state)
{
    unsigned long i;

    /* CLEAR VCFG AND DCFG */

    WRITE_VID32 (DF_VIDEO_CONFIG,   0);
    WRITE_VID32 (DF_DISPLAY_CONFIG, 0);

    /* RESTORE DF MSRS */

    msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CAP,    &(df_state->msr_cap));
    msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &(df_state->msr_config));
    msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_SMI,    &(df_state->msr_smi));
    msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_ERROR,  &(df_state->msr_error));
    msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_PM,     &(df_state->msr_pm));
    msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_DIAG,   &(df_state->msr_diag));
    msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF,   &(df_state->msr_df_diag));
    msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL,       &(df_state->msr_pad_sel));

    /* RESTORE ALL DF REGISTERS */

    WRITE_VID32 (DF_VIDEO_X_POS,           df_state->video_x);
    WRITE_VID32 (DF_VIDEO_Y_POS,           df_state->video_y);
    WRITE_VID32 (DF_VIDEO_SCALER,          df_state->video_scaler);
    WRITE_VID32 (DF_VIDEO_COLOR_KEY,       df_state->video_color_key);
    WRITE_VID32 (DF_VIDEO_COLOR_MASK,      df_state->video_color_mask);
    WRITE_VID32 (DF_SATURATION_LIMIT,      df_state->sat_limit);
    WRITE_VID32 (DF_VID_MISC,              df_state->vid_misc);
    WRITE_VID32 (DF_VIDEO_YSCALE,          df_state->video_yscale);
    WRITE_VID32 (DF_VIDEO_XSCALE,          df_state->video_xscale);
    WRITE_VID32 (DF_VID_ALPHA_CONTROL,     df_state->vid_alpha_control);
    WRITE_VID32 (DF_CURSOR_COLOR_KEY,      df_state->cursor_key);
    WRITE_VID32 (DF_CURSOR_COLOR_MASK,     df_state->cursor_mask);
    WRITE_VID32 (DF_CURSOR_COLOR_1,        df_state->cursor_color1);
    WRITE_VID32 (DF_CURSOR_COLOR_2,        df_state->cursor_color2);
    WRITE_VID32 (DF_ALPHA_XPOS_1,          df_state->alpha_xpos1);
    WRITE_VID32 (DF_ALPHA_YPOS_1,          df_state->alpha_ypos1);
    WRITE_VID32 (DF_ALPHA_COLOR_1,         df_state->alpha_color1);
    WRITE_VID32 (DF_ALPHA_CONTROL_1,       df_state->alpha_control1);
    WRITE_VID32 (DF_ALPHA_XPOS_2,          df_state->alpha_xpos2);
    WRITE_VID32 (DF_ALPHA_YPOS_2,          df_state->alpha_ypos2);
    WRITE_VID32 (DF_ALPHA_COLOR_2,         df_state->alpha_color2);
    WRITE_VID32 (DF_ALPHA_CONTROL_2,       df_state->alpha_control1);
    WRITE_VID32 (DF_ALPHA_XPOS_3,          df_state->alpha_xpos3);
    WRITE_VID32 (DF_ALPHA_YPOS_3,          df_state->alpha_ypos3);
    WRITE_VID32 (DF_ALPHA_COLOR_3,         df_state->alpha_color3);
    WRITE_VID32 (DF_ALPHA_CONTROL_3,       df_state->alpha_control3);
    WRITE_VID32 (DF_VIDEO_REQUEST,         df_state->vid_request);
    WRITE_VID32 (DF_VID_YPOS_EVEN,         df_state->vid_ypos_even);
    WRITE_VID32 (DF_VID_ALPHA_Y_EVEN_1,    df_state->alpha_ypos_even1);
    WRITE_VID32 (DF_VID_ALPHA_Y_EVEN_2,    df_state->alpha_ypos_even2);
    WRITE_VID32 (DF_VID_ALPHA_Y_EVEN_3,    df_state->alpha_ypos_even3);
    WRITE_VID32 (DF_VIDEO_PANEL_TIM1,      df_state->panel_tim1);
    WRITE_VID32 (DF_VIDEO_PANEL_TIM2,      df_state->panel_tim2);
    WRITE_VID32 (DF_POWER_MANAGEMENT,      df_state->panel_pm);
    WRITE_VID32 (DF_DITHER_CONTROL,        df_state->panel_dither);

    /* RESTORE DF PALETTE */

    WRITE_VID32 (DF_PALETTE_ADDRESS, 0);
	for (i = 0; i < 256; i++)
        WRITE_VID32 (DF_PALETTE_DATA, df_state->palette[i]);

    /* RESTORE FILTER COEFFICIENTS */

    for (i = 0; i < 512; i++)
        WRITE_VID32 (DF_COEFFICIENT_BASE + (i << 2), df_state->coefficients[i]);

    /* RESTORE DCFG AND VCFG */

    WRITE_VID32 (DF_DISPLAY_CONFIG, df_state->dcfg);
    WRITE_VID32 (DF_VIDEO_CONFIG, df_state->vcfg);

    return CIM_STATUS_OK;
}

/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 * CIMARRON DF READ ROUTINES
 * These routines are included for use in diagnostics or when debugging.  They
 * can be optionally excluded from a project.
 *+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/

#if CIMARRON_INCLUDE_DF_READ_ROUTINES

/*---------------------------------------------------------------------------
 * df_read_composite_crc
 *
 * This routine reads the CRC of the combination of graphics/video data.  This
 * CRC checks data immediately before the CRT DACs.
 *---------------------------------------------------------------------------*/

unsigned long df_read_composite_crc (int crc_source)
{
    Q_WORD msr_value;
	unsigned long crc;
    unsigned long interlaced;
    unsigned long line, field;
    unsigned long timeout = 1000;

	if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN))
		return 0xFFFFFFFF;

	/* ENABLE 32-BIT CRCS */

	msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &msr_value);
	msr_value.low |= DF_DIAG_32BIT_CRC;
	msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &msr_value);

	/* RESET THE CRC */

    WRITE_VID32 (DF_VID_CRC, 0);

    /* WAIT FOR THE RESET TO BE LATCHED */

    while ((READ_VID32 (DF_VID_CRC32) != 0x00000001) && timeout)
        timeout--;

    /* WAIT FOR THE CORRECT FIELD */
    /* We use the VG line count and field indicator to determine when */
    /* to kick off a CRC.                                             */

    if (crc_source & DF_CRC_SOURCE_EVEN) field = 0;
    else                                 field = DC3_LNCNT_EVEN_FIELD;

    if ((interlaced = (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN)))
    {
        /* WAIT FOR THE BEGINNING OF THE FIELD (LINE 1-5) */
        /* Note that we wait for the field to be odd when CRCing the even */
        /* field and vice versa.  This is because the CRC will not begin  */
        /* until the following field.                                     */

        do
        {
            line = READ_REG32 (DC3_LINE_CNT_STATUS);
        } while ((line & DC3_LNCNT_EVEN_FIELD) != field    ||
                ((line & DC3_LNCNT_V_LINE_CNT) >> 16) < 10 ||
                ((line & DC3_LNCNT_V_LINE_CNT) >> 16) > 15);
    }
    else
    {
        /* NON-INTERLACED - EVEN FIELD CRCS ARE INVALID */

        if (crc_source & DF_CRC_SOURCE_EVEN)
            return 0xFFFFFFFF;
    }

    /* ENABLE THE CRC */

	WRITE_VID32 (DF_VID_CRC, 1);

	/* WAIT FOR THE CRC TO BE COMPLETED */
	
    while (!(READ_VID32 (DF_VID_CRC) & 4))
        ;
	
	crc = READ_VID32 (DF_VID_CRC32);

	return crc;
}

/*---------------------------------------------------------------------------
 * df_read_composite_window_crc
 *
 * This routine reads the CRC of a rectangular subsection of the combination
 * of graphics/video data.
 *---------------------------------------------------------------------------*/

unsigned long df_read_composite_window_crc (unsigned long x, unsigned long y,
	unsigned long width, unsigned long height, int source)
{
    Q_WORD msr_value;
    unsigned long interlaced;
    unsigned long line, field;
	unsigned long crc = 0;
	unsigned long hsyncend, htotal, hsyncstart;
	unsigned long vsyncend, vtotal, vsyncstart;
    unsigned long hblankstart, hactive;
    unsigned long vblankstart, vactive;

    hsyncend    = ((READ_REG32 (DC3_H_SYNC_TIMING)   >> 16) & 0xFFF) + 1;
    htotal      = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1;
    hsyncstart  =  (READ_REG32 (DC3_H_SYNC_TIMING) & 0xFFF) + 1;
    hactive     =  (READ_REG32 (DC3_H_ACTIVE_TIMING) & 0xFFF) + 1;
    hblankstart =  (READ_REG32 (DC3_H_BLANK_TIMING)  & 0xFFF) + 1;
    if ((interlaced = (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN)) &&
        !(source & DF_CRC_SOURCE_EVEN))
    {
        vsyncend    = ((READ_REG32 (DC3_V_SYNC_EVEN)   >> 16) & 0xFFF) + 1;
	    vtotal      = ((READ_REG32 (DC3_V_ACTIVE_EVEN) >> 16) & 0xFFF) + 1;
	    vsyncstart  =  (READ_REG32 (DC3_V_SYNC_EVEN) & 0xFFF) + 1;
        vactive     =  (READ_REG32 (DC3_V_ACTIVE_EVEN) & 0xFFF) + 1;
        vblankstart =  (READ_REG32 (DC3_V_BLANK_EVEN)  & 0xFFF) + 1;
    }
    else
    {	
	    vsyncend    = ((READ_REG32 (DC3_V_SYNC_TIMING)   >> 16) & 0xFFF) + 1;
	    vtotal      = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1;
	    vsyncstart  =  (READ_REG32 (DC3_V_SYNC_TIMING) & 0xFFF) + 1;
        vactive     =  (READ_REG32 (DC3_V_ACTIVE_TIMING) & 0xFFF) + 1;
        vblankstart =  (READ_REG32 (DC3_V_BLANK_TIMING)  & 0xFFF) + 1;
    }

    /* TIMINGS MUST BE ACTIVE */

	if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN))
		return 0xFFFFFFFF;

    /* DISABLE GLCP ACTIONS */

    msr_value.low  = 0;
    msr_value.high = 0;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DIAGCTL, &msr_value);

	/* ENABLE HW CLOCK GATING AND SET GLCP CLOCK TO DOT CLOCK */

	msr_value.low = 5;
	msr_write64 (MSR_DEVICE_GEODELX_GLCP, MSR_GEODELINK_PM, &msr_value);
	msr_value.low = 0;
	msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value);
	msr_value.low = 3;
	msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value);

    /* USE H4 FUNCTION A FOR HSYNC AND H4 FUNCTION B FOR NOT HSYNC */
    /* HSYNC is bit 30 for the DF                                  */

    msr_value.high = 0x00000001;
    msr_value.low  = 0xE0000FF0;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 4, &msr_value);

    /* USE H3 FUNCTION A FOR VSYNC AND H3 FUNCTION B FOR NOT VSYNC */
    /* VSYNC is bit 54 for VG and bit 29 for DF                    */

    msr_value.high = 0x00000000;
    msr_value.low  = 0x001D55AA;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 3, &msr_value);

    /* M4 (XSTATE = 00 AND VSYNC HIGH) */
    /* Goto state 01                   */
    /* Note: VSync = H3A               */

    msr_value.high = 0x00000001;
    msr_value.low  = 0x000000A0;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL + 4, &msr_value);

    /* N0 (XSTATE = 01 AND VSYNC LOW) */
    /* Goto state 02                  */
    /* Note: VSync low = H3B          */

    msr_value.high = 0x00040000;
    msr_value.low  = 0x000000C0;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL, &msr_value);

    /* M5 (XSTATE = 10 AND VSYNC HIGH) */
    /* Goto state 11                   */

    msr_value.high = 0x00000001;
    msr_value.low  = 0x00000120;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL + 5, &msr_value);

    /* N1 (XSTATE = 10 and HSYNC LOW) */
    /* Increment H. Counter           */
    /* Note: HSync = H4               */

    msr_value.high = 0x00080000;
    msr_value.low  = 0x00000120;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 1, &msr_value);

    /* M0 (XSTATE = 10 and H. COUNTER == LIMIT)  */
    /* Clear H. Counter and increment V. Counter */

    msr_value.high = 0x00000000;
    msr_value.low  = 0x00000122;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL, &msr_value);

    /* N4 (XSTATE = 10 && CMP0 <= H. COUNTER <= CMP1 && CMP2 <= V. COUNTER <= CMP3) */
    /* CRC into REGB                                                                */

    msr_value.high = 0x00000000;
    msr_value.low  = 0x10C20120;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 4, &msr_value);

    /* COMPARATOR 0 VALUE                                   */
    /* Value = xstart + (htotal - hsync_end) - 1            */
    /* The value will be adjusted for a border if necessary */

    msr_value.low  = x + htotal - hsyncend - 1;
    if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DCEN)
        msr_value.low -= hblankstart - hactive;
    msr_value.low--;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0, &msr_value);

    /* COMPARATOR 1 VALUE                                    */
    /* Value = xstart + (htotal - hsync_end - 1) - 1 + width */

    msr_value.low  += width - 1;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 2, &msr_value);

    /* COMPARATOR 2 VALUE                 */
    /* Value = ystart + vtotal - vsyncend */

    msr_value.low  = (y + vtotal - vsyncend) << 16;
    if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DCEN)
        msr_value.low -= (vblankstart - vactive) << 16;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 4, &msr_value);

    /* COMPARATOR 3 VALUE                              */
    /* Value = ystart + vtotal - vsyncend + height - 1 */

    msr_value.low  += (height - 1) << 16;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 6, &msr_value);

    /* COMPARATOR MASKS */
    /* Comparators 0 and 1 refer to lower 16 bits of RegB */

    msr_value.low = 0x0000FFFF;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0, &msr_value);
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 2, &msr_value);

    /* Comparators 2 and 3 refer to upper 16 bits of RegB */

    msr_value.low = 0xFFFF0000;
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 4, &msr_value);
    msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 6, &msr_value);

    /* SET REGB MASK                                                */
    /* We set the mask such that all only 24 bits of data are CRCed */

    msr_value.low = 0x00FFFFFF;
    msr_write64 (MSR_DEVICE_GEODELX