📄 cim_df.c
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unsigned long scale, coeff0, coeff1;
unsigned long i;
long (*defaults)[2];
/* SET PHASE COUNT AND CHOOSE COEFFICIENT ARRAY */
scale = READ_VID32 (DF_VIDEO_SCALER);
if (phase256)
{
WRITE_VID32 (DF_VIDEO_SCALER, (scale & ~DF_SCALE_128_PHASES));
defaults = CimarronVideoFilter256;
}
else
{
WRITE_VID32 (DF_VIDEO_SCALER, (scale | DF_SCALE_128_PHASES));
defaults = CimarronVideoFilter128;
}
/* PROGRAM COEFFICIENTS */
for (i = 0; i < 256; i++)
{
if (!taps)
{
coeff0 = defaults[i][0];
coeff1 = defaults[i][1];
}
else
{
if (taps[i][1] < 0) coeff0 = -taps[i][1] | 0x8000;
else coeff0 = taps[i][1];
coeff0 <<= 16;
if (taps[i][0] < 0) coeff0 |= -taps[i][0] | 0x8000;
else coeff0 |= taps[i][0];
if (taps[i][3] < 0) coeff1 = -taps[i][3] | 0x8000;
else coeff1 = taps[i][3];
coeff1 <<= 16;
if (taps[i][2] < 0) coeff1 |= -taps[i][2] | 0x8000;
else coeff1 |= taps[i][2];
}
WRITE_VID32 ((DF_COEFFICIENT_BASE + (i << 3)), coeff0);
WRITE_VID32 ((DF_COEFFICIENT_BASE + (i << 3) + 4), coeff1);
}
return CIM_STATUS_OK;
}
/*---------------------------------------------------------------------------
* df_set_video_enable
*
* This routine enables or disables the video overlay.
*---------------------------------------------------------------------------*/
int df_set_video_enable (int enable, unsigned long flags)
{
unsigned long vcfg, lock, gcfg;
unsigned long dcfg, vg_ckey, fifo = 0;
vcfg = READ_VID32 (DF_VIDEO_CONFIG);
lock = READ_REG32 (DC3_UNLOCK);
gcfg = READ_REG32 (DC3_GENERAL_CFG);
/* SET VIDEO FIFO END WATERMARK */
/* The video FIFO end watermark is set to 0 when video is disabled */
/* to allow low priority transactions in the VG. Otherwise, the */
/* priority will be forced high until the VG fills the video FIFO */
/* by not fetching video. That could take a while... Note that */
/* we set the end priority to be 4 greater than the start. We */
/* assume that the start priority has been configured by a modeset. */
dcfg = READ_REG32 (DC3_DISPLAY_CFG) & ~DC3_DCFG_VFHPEL_MASK;
if (enable)
{
fifo = ((dcfg >> 12) & 0x0000000F) + 4;
if (fifo > 0xF)
fifo = 0xF;
}
WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE);
WRITE_REG32 (DC3_DISPLAY_CFG, dcfg | (fifo << 16));
/* ENABLE OR DISABLE VIDEO */
/* The mechanism to fetch video data is enabled first and */
/* disabled last. */
if (enable)
{
WRITE_REG32 (DC3_GENERAL_CFG, (gcfg | DC3_GCFG_VIDE));
WRITE_VID32 (DF_VIDEO_CONFIG, (vcfg | DF_VCFG_VID_EN));
/* DISABLE COLOR KEYING IF REQUESTED BY THE USER */
if (flags & DF_ENABLEFLAG_NOCOLORKEY)
{
/* OVERRIDE THE MODE TO COLOR KEYING */
dcfg = READ_VID32 (DF_DISPLAY_CONFIG);
WRITE_VID32 (DF_DISPLAY_CONFIG, (dcfg & ~DF_DCFG_VG_CK));
/* DISABLE COLOR KEYING IN THE VG */
vg_ckey = READ_REG32 (DC3_COLOR_KEY);
WRITE_REG32 (DC3_COLOR_KEY, (vg_ckey & ~DC3_CLR_KEY_ENABLE));
}
else if (!(READ_VID32 (DF_DISPLAY_CONFIG) & DF_DCFG_VG_CK))
{
/* OTHERWISE RE-ENABLE COLOR KEYING */
vg_ckey = READ_REG32 (DC3_COLOR_KEY);
WRITE_REG32 (DC3_COLOR_KEY, (vg_ckey | DC3_CLR_KEY_ENABLE));
}
}
else
{
WRITE_VID32 (DF_VIDEO_CONFIG, (vcfg & ~DF_VCFG_VID_EN));
WRITE_REG32 (DC3_GENERAL_CFG, (gcfg & ~DC3_GCFG_VIDE));
/* DISABLE COLOR KEY WINDOW WHEN VIDEO IS INACTIVE */
/* To mimic legacy functionality, we disble color keying */
/* when the video window is not active. We will restore */
/* the enable when video is re-enabled if the appropriate */
/* bit is set in display config. */
vg_ckey = READ_REG32 (DC3_COLOR_KEY);
WRITE_REG32 (DC3_COLOR_KEY, (vg_ckey & ~DC3_CLR_KEY_ENABLE));
}
WRITE_REG32 (DC3_UNLOCK, lock);
return CIM_STATUS_OK;
}
/*---------------------------------------------------------------------------
* df_set_video_color_key
*
* This routine configures the video color/chroma key mechanism.
*---------------------------------------------------------------------------*/
int df_set_video_color_key (unsigned long key, unsigned long mask, int graphics)
{
unsigned long lock, vg_ckey, df_dcfg;
vg_ckey = READ_REG32 (DC3_COLOR_KEY);
lock = READ_REG32 (DC3_UNLOCK);
df_dcfg = READ_VID32 (DF_DISPLAY_CONFIG);
WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE);
if (graphics)
{
/* COLOR KEY - USE VG HARDWARE */
/* Note that color key is never enabled unless a video window */
/* is active. This is to match legacy behavior. */
df_dcfg &= ~DF_DCFG_VG_CK;
vg_ckey = (vg_ckey & 0xFF000000) | (key & 0xFFFFFF);
if (READ_VID32 (DF_VIDEO_CONFIG) & DF_VCFG_VID_EN)
vg_ckey |= DC3_CLR_KEY_ENABLE;
else
vg_ckey &= ~DC3_CLR_KEY_ENABLE;
WRITE_VID32 (DF_DISPLAY_CONFIG, df_dcfg);
WRITE_REG32 (DC3_COLOR_KEY, vg_ckey);
WRITE_REG32 (DC3_COLOR_MASK, (mask & 0xFFFFFF));
}
else
{
/* CHROMA KEY - USE DF HARDWARE */
df_dcfg |= DF_DCFG_VG_CK;
vg_ckey &= ~DC3_CLR_KEY_ENABLE;
WRITE_REG32 (DC3_COLOR_KEY, vg_ckey);
WRITE_VID32 (DF_DISPLAY_CONFIG, df_dcfg);
WRITE_VID32 (DF_VIDEO_COLOR_KEY, (key & 0xFFFFFF));
WRITE_VID32 (DF_VIDEO_COLOR_MASK, (mask & 0xFFFFFF));
}
WRITE_REG32 (DC3_UNLOCK, lock);
return CIM_STATUS_OK;
}
/*---------------------------------------------------------------------------
* df_set_video_palette
*
* This routine loads the video hardware palette. If a NULL pointer is
* specified, the palette is bypassed.
*--------------------------------------------------------------------------*/
int df_set_video_palette (unsigned long *palette)
{
unsigned long i, entry;
unsigned long misc, dcfg;
/* LOAD GEODE LX VIDEO PALETTE */
WRITE_VID32 (DF_PALETTE_ADDRESS, 0);
for (i = 0; i < 256; i++)
{
if (palette) entry = palette[i];
else entry = i | (i << 8) | (i << 16);
WRITE_VID32 (DF_PALETTE_DATA, entry);
}
/* ENABLE THE VIDEO PALETTE */
/* Ensure that the video palette has an effect by routing video data */
/* through the palette RAM and clearing the 'Bypass Both' bit. */
dcfg = READ_VID32 (DF_DISPLAY_CONFIG);
misc = READ_VID32 (DF_VID_MISC);
dcfg |= DF_DCFG_GV_PAL_BYP;
misc &= ~DF_GAMMA_BYPASS_BOTH;
WRITE_VID32 (DF_DISPLAY_CONFIG, dcfg);
WRITE_VID32 (DF_VID_MISC, misc);
return CIM_STATUS_OK;
}
/*---------------------------------------------------------------------------
* df_set_video_palette_entry
*
* This routine loads a single entry of the video hardware palette.
*--------------------------------------------------------------------------*/
int df_set_video_palette_entry (unsigned long index, unsigned long palette)
{
unsigned long misc, dcfg;
if (index > 0xFF)
return CIM_STATUS_INVALIDPARAMS;
/* SET A SINGLE ENTRY */
WRITE_VID32 (DF_PALETTE_ADDRESS, index);
WRITE_VID32 (DF_PALETTE_DATA, palette);
/* ENABLE THE VIDEO PALETTE */
/* Ensure that the video palette has an effect by routing video data */
/* through the palette RAM and clearing the 'Bypass Both' bit. */
dcfg = READ_VID32 (DF_DISPLAY_CONFIG);
misc = READ_VID32 (DF_VID_MISC);
dcfg |= DF_DCFG_GV_PAL_BYP;
misc &= ~DF_GAMMA_BYPASS_BOTH;
WRITE_VID32 (DF_DISPLAY_CONFIG, dcfg);
WRITE_VID32 (DF_VID_MISC, misc);
return CIM_STATUS_OK;
}
/*---------------------------------------------------------------------------
* df_configure_video_cursor_color_key
*
* This routine configures the hardware video cursor color key mechanism.
*--------------------------------------------------------------------------*/
int df_configure_video_cursor_color_key (DF_VIDEO_CURSOR_PARAMS *cursor_color_key)
{
unsigned long key;
if (cursor_color_key->select_color2 >= 24)
return CIM_STATUS_INVALIDPARAMS;
key = READ_VID32 (DF_CURSOR_COLOR_KEY) & DF_CURSOR_COLOR_KEY_ENABLE;
key = key | (cursor_color_key->key & 0xFFFFFF) | (cursor_color_key->select_color2 << 24);
WRITE_VID32 (DF_CURSOR_COLOR_KEY, key);
WRITE_VID32 (DF_CURSOR_COLOR_MASK, (cursor_color_key->mask & 0xFFFFFF));
WRITE_VID32 (DF_CURSOR_COLOR_1, (cursor_color_key->color1 & 0xFFFFFF));
WRITE_VID32 (DF_CURSOR_COLOR_2, (cursor_color_key->color2 & 0xFFFFFF));
return CIM_STATUS_OK;
}
/*---------------------------------------------------------------------------
* df_set_video_cursor_color_key_enable
*
* This routine enables or disables the video cursor color key.
*--------------------------------------------------------------------------*/
int df_set_video_cursor_color_key_enable (int enable)
{
unsigned long temp = READ_VID32 (DF_CURSOR_COLOR_KEY);
if (enable) temp |= DF_CURSOR_COLOR_KEY_ENABLE;
else temp &= ~DF_CURSOR_COLOR_KEY_ENABLE;
WRITE_VID32 (DF_CURSOR_COLOR_KEY, temp);
return CIM_STATUS_OK;
}
/*---------------------------------------------------------------------------
* df_configure_alpha_window
*
* This routine configures one of the three hardware alpha regions.
*--------------------------------------------------------------------------*/
int df_configure_alpha_window (int window, DF_ALPHA_REGION_PARAMS *alpha_data)
{
unsigned long vsyncend_even, vtotal_even, vactive_even;
unsigned long hsyncend, htotal, hactive;
unsigned long vsyncend, vtotal, vactive;
unsigned long alpha_ctl, pos;
unsigned long hadjust, vadjust;
unsigned long y, height;
unsigned long xstart, xend;
unsigned long ystart, yend;
unsigned long x_copy, width_copy;
unsigned long y_copy, height_copy;
unsigned long scale, src, misc;
unsigned long gfxscale, fbactive;
unsigned long color;
if (window > 2)
return CIM_STATUS_INVALIDPARAMS;
hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1;
vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1;
hactive = (READ_REG32 (DC3_H_ACTIVE_TIMING) & 0xFFF) + 1;
vactive = (READ_REG32 (DC3_V_ACTIVE_TIMING) & 0xFFF) + 1;
/* APPLY THE GRAPHICS SCALE */
width_copy = alpha_data->width;
height_copy = alpha_data->height;
x_copy = alpha_data->x;
y_copy = alpha_data->y;
misc = READ_VID32 (DF_VID_MISC);
if (misc & DF_USER_IMPLICIT_SCALING)
{
gfxscale = READ_REG32 (DC3_GFX_SCALE);
fbactive = READ_REG32 (DC3_FB_ACTIVE);
/* REVERSE ENGINEER THE SCALE FACTOR */
scale = gfxscale & 0xFFFF;
src = (fbactive >> 16) + 1;
if (scale != 0x4000)
{
width_copy = width_copy * (((0x4000 * src) / scale) + 1);
width_copy /= src;
x_copy = x_copy * (((0x4000 * src) / scale) + 1);
x_copy /= src;
}
scale = gfxscale >> 16;
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