_primary.vhd

DMA Directly memory access

library verilog;
use verilog.vl_types.all;
entity DMA is
    port(
        cs              : in     vl_logic;
        ck              : in     vl_logic;
        reset           : in     vl_logic;
        wr              : in     vl_logic;
        rd              : in     vl_logic;
        avalon_add      : in     vl_logic_vector(3 downto 0);
        data_out        : out    vl_logic_vector(31 downto 0);
        avalon_data     : in     vl_logic_vector(31 downto 0);
        MasterRead_read_data: in     vl_logic_vector(31 downto 0);
        read_wait_request: in     vl_logic;
        MasterRead_add  : out    vl_logic_vector(31 downto 0);
        MasterRead_read : out    vl_logic;
        write_wait_request: in     vl_logic;
        MasterWrite_add : out    vl_logic_vector(31 downto 0);
        MasterWrite_write_data: out    vl_logic_vector(31 downto 0);
        MasterWrite_write: out    vl_logic
    );
end DMA;