📄 pc1interrupt.txt
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#include "global.h"
#include "interrupt.h"
static cyg_interrupt int1;
static cyg_handle_t int1_handle;
static cyg_interrupt int2;
static cyg_handle_t int2_handle;
static cyg_sem_t data_ready;
int g_currentInterruptState=RISING;
int g_bKeyInterrupt=0;
void SetEXTI0Edge(int edge)
{
int acr=0;
CYG_ADDRESS base = CYGHWR_HAL_STM32_EXTI;
if(edge==FALLING)
{
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_FTSR, acr );
acr|=0x00000001;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_FTSR,acr);
}
else if(edge==RISING)
{
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_RTSR, acr );
acr|=0x00000001;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_RTSR,acr);
}
}
// Interrupt service routine for interrupt 1.
cyg_uint32 interrupt_1_isr( cyg_uint32 vector, CYG_ADDRWORD data )
{
int acr=0;
CYG_ADDRESS base = CYGHWR_HAL_STM32_EXTI;
if(g_currentInterruptState==RISING)
{
g_currentInterruptState=FALLING;
//EnableDisableTIM2Counter(ENABLE);
}
else
{
g_currentInterruptState=RISING;
//EnableDisableTIM2Counter(DISABLE);
}
SetEXTI0Edge(g_currentInterruptState);
g_bKeyInterrupt=1;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_PR,0x00000001);
// Block this interrupt from occurring until the DSR completes.
//cyg_interrupt_mask( CYGNUM_HAL_INTERRUPT_EXTI0 );
// Tell the processor that we have received the interrupt.
cyg_interrupt_acknowledge( vector );
// Tell the kernel that chained interrupt processing
// is done and the DSR needs to be executed next.
return CYG_ISR_HANDLED ;
}
void interrupt_1_dsr( cyg_uint32 vector,CYG_ADDRWORD data )
{
}
void interrupt_1_handler(void)
{
unsigned long int base;
unsigned int acr,i=0;
int crl;
int cur=0;
cyg_vector_t int1_vector = CYGNUM_HAL_INTERRUPT_EXTI0;
cyg_priority_t int1_priority = CYGNUM_HAL_PRI_HIGH;
// Enable all devices in RCC
base = CYGHWR_HAL_STM32_RCC;
HAL_READ_UINT32(base+CYGHWR_HAL_STM32_RCC_CFGR,acr);
#ifdef MYDBG
printf("\nRCC_CFGR= %x %d\n",acr,__LINE__);
#endif
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR,0xFFFFFFFF);
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB1ENR,0xFFFFFFFF);
// Create interrupt 1.
//cyg_semaphore_init( &data_ready, 0 );
cyg_interrupt_create(int1_vector,int1_priority,0,&interrupt_1_isr,&interrupt_1_dsr,&int1_handle,&int1);
// Attach the interrupt created to the vector.
cyg_interrupt_attach( int1_handle );
// Tell the processor that we have received the interrupt.
cyg_interrupt_acknowledge(int1_vector);
// Unmask the interrupt we just configured.
cyg_interrupt_unmask( int1_vector );
cyg_interrupt_enable();
//Set up GPIO-A Port lines to input mode and Pullup/PullDown Input
base = CYGHWR_HAL_STM32_GPIOA;
HAL_READ_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, crl);
// crl = crl & (~0x000000F0);
// crl = crl | 0x00000080;
crl = crl & (~0x0000000F);
crl = crl | 0x00000008;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, crl);
//HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0X88883388 );
// HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x888884b4 );
//Setting External interrupt configuration register 1 (AFIO_EXTICR1) to
// have source input as GPIO-A port.
base = CYGHWR_HAL_STM32_AFIO;
HAL_WRITE_UINT32( base+ AFIO_EXTICR1 ,0x00000000 );
//Set up Interrupt on wake button
base= CYGHWR_HAL_STM32_EXTI;
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_IMR, acr );
acr|=0x00000001;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_IMR,acr ); //1. Set EXTI_IMR Register.
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_RTSR, acr );
acr|=0x00000001;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_RTSR,0x00000001); //2. Set EXTI_RTSR Register.
//HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_FTSR, acr );
//acr|=0x00000001;
//HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_FTSR,acr);
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_PR, acr );
acr|=0x00000001;
HAL_WRITE_UINT32( base+ CYGHWR_HAL_STM32_EXTI_PR, acr); //3. Clear EXTI_PR Register
}
/*vipul- change for ISR*/
void interrupt_2_handler(void)
{
unsigned long int base;
unsigned int acr,i=0;
int crl;
int cur=0;
cyg_vector_t int2_vector = CYGNUM_HAL_INTERRUPT_EXTI1;
cyg_priority_t int2_priority = CYGNUM_HAL_PRI_HIGH;
// Enable all devices in RCC
base = CYGHWR_HAL_STM32_RCC;
HAL_READ_UINT32(base+CYGHWR_HAL_STM32_RCC_CFGR,acr);
#ifdef MYDBG
printf("\nRCC_CFGR= %x %d\n",acr,__LINE__);
#endif
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR,0xFFFFFFFF);
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB1ENR,0xFFFFFFFF);
// Create interrupt 1.
//cyg_semaphore_init( &data_ready, 0 );
cyg_interrupt_create(int2_vector,int2_priority,0,&interrupt_2_isr,&interrupt_2_dsr,&int2_handle,&int2);
// Attach the interrupt created to the vector.
cyg_interrupt_attach( int2_handle );
// Tell the processor that we have received the interrupt.
cyg_interrupt_acknowledge(int2_vector);
// Unmask the interrupt we just configured.
cyg_interrupt_unmask( int2_vector );
cyg_interrupt_enable();
//Set up GPIO-A Port lines to input mode and Pullup/PullDown Input
base = CYGHWR_HAL_STM32_GPIOC;
HAL_READ_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, crl);
crl = crl & (~0x000000F0);
crl = crl | 0x00000080;
//crl = crl & (~0x0000000F);
//crl = crl | 0x00000008;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, crl);
//HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0X88883388 );
// HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x888884b4 );
//
//Setting External interrupt configuration register 1 (AFIO_EXTICR1) to
// have source input as GPIO-C port.
base = CYGHWR_HAL_STM32_AFIO;
HAL_WRITE_UINT32( base+ AFIO_EXTICR1 ,0x00000020 );
//Set up Interrupt on wake button
base= CYGHWR_HAL_STM32_EXTI;
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_IMR, acr );
acr|=0x00000002;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_IMR,acr ); //1. Set EXTI_IMR Register.
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_FTSR, acr );
acr|=0x00000002;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_FTSR,0x00000002); //2. Set EXTI_FTSR Register.
//HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_FTSR, acr );
//acr|=0x00000001;
//HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_FTSR,acr);
HAL_READ_UINT32( base+ CYGHWR_HAL_STM32_EXTI_PR, acr );
acr|=0x00000002;
HAL_WRITE_UINT32( base+ CYGHWR_HAL_STM32_EXTI_PR, acr); //3. Clear EXTI_PR Register
}
// Interrupt service routine for interrupt 1.
cyg_uint32 interrupt_2_isr( cyg_uint32 vector, CYG_ADDRWORD data )
{
int acr=0;
CYG_ADDRESS base = CYGHWR_HAL_STM32_EXTI;
printf("\nenter into the interrupt------\n");
/* if(g_currentInterruptState==RISING)
{
g_currentInterruptState=FALLING;
//EnableDisableTIM2Counter(ENABLE);
}
else
{
g_currentInterruptState=RISING;
//EnableDisableTIM2Counter(DISABLE);
}*/
//SetEXTI0Edge(g_currentInterruptState);
//g_bKeyInterrupt=1;
// Clear the EXTI1
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_EXTI_PR,0x00000002);
// Block this interrupt from occurring until the DSR completes.
//cyg_interrupt_mask( CYGNUM_HAL_INTERRUPT_EXTI0 );
// Tell the processor that we have received the interrupt.
cyg_interrupt_acknowledge( vector );
// Tell the kernel that chained interrupt processing
// is done and the DSR needs to be executed next.
return CYG_ISR_HANDLED ;
}
void interrupt_2_dsr( cyg_uint32 vector,CYG_ADDRWORD data )
{
}
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