📄 c8051f120.h
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/* CPT0CN 0x88 */sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE *//* CPT1CN 0x88 */sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE *//* FLSTAT 0x88 */sbit at 0x88 FLHBUSY ; /* FLASH BUSY *//* SCON0 0x98 */sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */sbit at 0x9C REN ; /* UART 0 RX ENABLE */sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */sbit at 0x9E SM10 ; /* UART 0 MODE 1 */sbit at 0x9F SM00 ; /* UART 0 MODE 0 *//* SCON1 0x98 */sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */sbit at 0x9D MCE1 ; /* UART 1 MCE */sbit at 0x9F S1MODE ; /* UART 1 MODE *//* IE 0xA8 */sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE *//* IP 0xB8 */sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY *//* SMB0CN 0xC0 */sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY *//* TMR2CN 0xC8 */sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG *//* TMR3CN 0xC8 */sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG *//* TMR4CN 0xC8 */sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG *//* P4 0xC8 */sbit at 0xC8 P4_0 ;sbit at 0xC9 P4_1 ;sbit at 0xCA P4_2 ;sbit at 0xCB P4_3 ;sbit at 0xCC P4_4 ;sbit at 0xCD P4_5 ;sbit at 0xCE P4_6 ;sbit at 0xCF P4_7 ;/* PSW 0xD0 */sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */sbit at 0xD1 F1 ; /* USER FLAG 1 */sbit at 0xD2 OV ; /* OVERFLOW FLAG */sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */sbit at 0xD5 F0 ; /* USER FLAG 0 */sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */sbit at 0xD7 CY ; /* CARRY FLAG *//* PCA0CN D8H */sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG *//* P5 0xD8 */sbit at 0xD8 P5_0 ;sbit at 0xD9 P5_1 ;sbit at 0xDA P5_2 ;sbit at 0xDB P5_3 ;sbit at 0xDC P5_4 ;sbit at 0xDD P5_5 ;sbit at 0xDE P5_6 ;sbit at 0xDF P5_7 ;/* ADC0CN E8H */sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */sbit at 0xEF AD0EN ; /* ADC 0 ENABLE *//* ADC2CN E8H */sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */sbit at 0xEF AD2EN ; /* ADC 2 ENABLE *//* P6 0xE8 */sbit at 0xE8 P6_0 ;sbit at 0xE9 P6_1 ;sbit at 0xEA P6_2 ;sbit at 0xEB P6_3 ;sbit at 0xEC P6_4 ;sbit at 0xED P6_5 ;sbit at 0xEE P6_6 ;sbit at 0xEF P6_7 ;/* SPI0CN F8H */sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG *//* P7 0xF8 */sbit at 0xF8 P7_0 ;sbit at 0xF9 P7_1 ;sbit at 0xFA P7_2 ;sbit at 0xFB P7_3 ;sbit at 0xFC P7_4 ;sbit at 0xFD P7_5 ;sbit at 0xFE P7_6 ;sbit at 0xFF P7_7 ;/* Predefined SFR Bit Masks */#define IDLE 0x01 /* PCON */#define STOP 0x02 /* PCON */#define ECCF 0x01 /* PCA0CPMn */#define PWM 0x02 /* PCA0CPMn */#define TOG 0x04 /* PCA0CPMn */#define MAT 0x08 /* PCA0CPMn */#define CAPN 0x10 /* PCA0CPMn */#define CAPP 0x20 /* PCA0CPMn */#define ECOM 0x40 /* PCA0CPMn */#define PWM16 0x80 /* PCA0CPMn */#define PORSF 0x02 /* RSTSRC */#define SWRSF 0x10 /* RSTSRC *//* SFR PAGE DEFINITIONS */#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */#define CPT0_PAGE 0x01 /* COMPARATOR 0 */#define CPT1_PAGE 0x02 /* COMPARATOR 1 */#define UART0_PAGE 0x00 /* UART 0 */#define UART1_PAGE 0x01 /* UART 1 */#define SPI0_PAGE 0x00 /* SPI 0 */#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */#define ADC0_PAGE 0x00 /* ADC 0 */#define ADC2_PAGE 0x02 /* ADC 2 */#define SMB0_PAGE 0x00 /* SMBUS 0 */#define TMR2_PAGE 0x00 /* TIMER 2 */#define TMR3_PAGE 0x01 /* TIMER 3 */#define TMR4_PAGE 0x02 /* TIMER 4 */#define DAC0_PAGE 0x00 /* DAC 0 */#define DAC1_PAGE 0x01 /* DAC 1 */#define PCA0_PAGE 0x00 /* PCA 0 */#define PLL0_PAGE 0x0F /* PLL 0 */#endif⌨️ 快捷键说明
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